MAX194BEWE+ Datasheet MAX194ACWE+, MAX194BEWE+, MAX194AEWE+ | P7-P9

If the power supplies do not settle within the MAX194’s

power-on delay (500ns minimum), power-up calibration

may begin with supply voltages that differ from the final

values and the converter may not be properly calibrat-

ed. If so, recalibrate the converter (pulse RESET low)

before use. For best DC accuracy, calibrate the

MAX194 any time there is a significant change in sup-

ply voltages, temperature, reference voltage, or clock

characteristics (see

External Clock

section) because

these parameters affect the DC offset. If linearity is the

only concern, much larger changes in these parame-

ters can be tolerated.

Because the calibration data is stored digitally, there is

no need either to perform frequent conversions to main-

tain accuracy or to recalibrate if the MAX194 has been

held in shutdown for long periods. However, recalibra-

tion is recommended if it is likely that supply voltages or

ambient temperature has significantly changed since

the previous calibration.

Digital Interface

The digital interface pins consist of BP/UP/SHDN, CLK,

SCLK, EOC, CS, CONV, and RESET.

BP/UP/SHDN is a three-level input. Leave it floating to

configure the MAX194’s analog input in bipolar mode

(AIN = -V

REF

to V

REF

) or connect it high for a unipolar

input (AIN = 0V to V

REF

). Bringing BP/UP/SHDN low

places the MAX194 in its 10µA shutdown mode.

A logic low on RESET halts MAX194 operation. The ris-

ing edge of RESET initiates calibration as described in

the

Calibration

section above.

Begin a conversion by bringing CONV low. The convert

signal must be synchronized with CLK. The falling edge

of CONV must occur during the period shown in

Figures 3 and 4. When CLK is not directly controlled by

your processor, two methods of ensuring synchroniza-

tion are to drive CONV from EOC (continuous conver-

sions) or to gate the conversion-start signal with the

conversion clock so that CONV can go low only while

CLK is low (Figure 5). Ensure that the maximum propa-

gation delay through the gate is less than 40ns.

The MAX194 automatically ensures four CLK periods

for track/hold acquisition. If, when CONV is asserted, at

least three clock (CLK) cycles have passed since the

end of the previous conversion, a conversion will begin

on CLK’s next falling edge and EOC will go high on the

following falling CLK edge (Figure 3). After conversion

begins, additional convert start pulses are ignored. If,

when convert is asserted, less than three clock cycles

have passed, a conversion will begin on the fourth

falling clock edge after the end of the previous conver-

MAX194

14-Bit, 85ksps ADC with 10µA Shutdown

_______________________________________________________________________________________ 7

TRACK/HOLD

CLK

CONVERSION

BEGINS

CONVERSION

ENDS

THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION

CEL

CEH

CC2

CC1

EOC

CONV

Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.

MAX194

sion and EOC will go high on the following CLK falling

edge (Figure 4). CONV is ignored during conversions.

External Clock

The conversion clock (CLK) should have a duty cycle

between 25% and 75% at 1.7MHz (the maximum clock

frequency). For lower frequency clocks, ensure the

minimum high and low times exceed 150ns. The mini-

mum clock rate for accurate conversion is 125Hz for

temperatures up to +70°C or 1kHz at +125°C due to

leakage of the sampling capacitor array. In addition,

CLK should not remain high longer than 50ms at tem-

peratures up to +70°C or 500µs at +125°C. If CLK is

held high longer than this, RESET must be pulsed low

to initiate a recalibration because it is possible that

state information stored in internal dynamic memory

may be lost. The MAX194’s clock can be stopped

indefinitely if it is held low.

If the frequency, duty cycle, or other aspects of the

clock signal’s shape change, the offset created by cou-

pling between CLK and the analog inputs (AIN and

REF) changes. Recalibration corrects for this offset and

restores DC accuracy.

Output Data

The conversion result is clocked out MSB first, format-

ted as 14 data bits plus two sub-LSBs. Serial data is

available on DOUT only when CS is held low.

Otherwise, DOUT is in a high-impedance state. There

are two ways to read the data on DOUT. To read the

data bits as they are determined (at the CLK clock

rate), hold CS low during the conversion. To read

results between conversions, hold CS low and clock

SCLK at up to 5MHz.

If you read the serial data bits as they are determined

(at the conversion-clock rate), EOC frames the data bits

(Figure 6). Conversion begins with the first falling CLK

edge, after CONV goes low and the input signal has

been acquired. Data bits are shifted out of DOUT on

subsequent falling CLK edges. Clock data in on CLK’s

rising edge or, if the clock speed is greater than 1MHz,

on the following falling edge of CLK to meet the maxi-

mum CLK-to-DOUT timing specification. See the

Operating Modes and SPI™/QSPI™ Interfaces

section

for additional information. Reading the serial data dur-

ing the conversion results in the maximum conversion

throughput, because a new conversion can begin

immediately after the input acquisition period following

the previous conversion.

14-Bit, 85ksps ADC with 10µA Shutdown

8 _______________________________________________________________________________________

TRACK/HOLD

CLK

CONVERSION

BEGINS

CONVERSION

ENDS

THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION

CEL

CEH

CC2

CC1

EOC

CONV

Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.

SPI/QSPI are trademarks of Motorola Corp.

If you read the data bits between conversions, you can

1) count CLK cycles until the end of the conversion, or

2) poll EOC to determine when the conversion is

finished, or

3) generate an interrupt on EOC’s falling edge.

Note that the MSB conversion result appears at DOUT

after CS goes low but before the first SCLK pulse. Each

subsequent SCLK pulse shifts out the next conversion

bit. The 15th SCLK pulse shifts out the sub-LSB (S0).

Additional clock pulses shift out zeros.

Data is clocked out on SCLK’s falling edge. Clock data

in on SCLK’s rising edge or, for clock speeds above

2.5MHz, on the following falling edge to meet the maxi-

mum SCLK-to-DOUT timing specification (Figure 7).

The maximum SCLK speed is 5MHz. See the

Operating

Modes and SPI/QSPI Interfaces

section for additional

information. When the conversion clock is near its maxi-

MAX194

14-Bit, 85ksps ADC with 10µA Shutdown

_______________________________________________________________________________________ 9

CLK

START

CONV

MAX194

CONV

START

CLK

SEE

DIGITAL INTERFACE

SECTION

CONV

CLK

(CASE 1)

CLK

(CASE 2)

EOC

CEH

CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)

CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)

NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE

CEL

DOUT

B13

CONVERSION

BEGINS

CONVERSION

ENDS

MSB LSB SUB-LSBs

B12 B11 B10 B0 S1 S0 B13

B13 FROM PREVIOUS

CONVERSION

Figure 5. Gating CONV to Synchronize with CLK

Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

MAX194BEWE+

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Analog to Digital Converters - ADC 14Bit 85ksps 5V Precision ADC

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