Advanced Clock Drivers Device Data
Freescale Semiconductor 11
MPC9773
Power Supply Filtering
The MPC9773 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the V
CC_PLL
power supply impacts the device
characteristics, for instance I/O jitter. The MPC9773 provides
separate power supplies for the output buffers (V
CC
) and the
phase-locked loop (V
CC_PLL
) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
V
CCA_PLL
pin for the MPC9773. Figure 7 illustrates a typical
power supply filter scheme. The MPC9773 frequency and
phase stability is most susceptible to noise with spectral
content in the 100-kHz to 20-MHz range. Therefore, the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor R
F
. From the data sheet
the I
CC_PLL
current (the current sourced through the V
CC_PLL
pin) is typically 8 mA (13.5 mA maximum), assuming that a
minimum of 3.0 V must be maintained on the V
CC_PLL
pin.
The resistor R
F
shown in Figure 7 must have a resistance of
5–10 Ω to meet the voltage drop criteria.
Figure 7. V
CC_PLL
Power Supply Filter
The minimum values for R
F
and the filter capacitor C
F
are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
4.5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9773 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9773 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9773. Designs using the MPC9773 as an LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9773 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge, resulting in a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or long-
term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9773 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9773 are connected together, the maximum overall
timing uncertainty from the common CCLKx input to any
output is:
t
SK(PP)
= t
(∅)
+ t
SK(O)
+ t
PD, LINE(FB)
+ t
JIT(∅)
∗ CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay, and I/O (phase) jitter:
Figure 8. MPC9773 Maximum Device-to-Device Skew
V
CC_PLL
V
CC
MPC9773
10 nF
R
F
= 5–10 Ω
C
F
33...100 nF
R
F
V
CC
C
F
= 22 µF
t
PD,LINE(FB)
t
JIT(∅)
+t
SK(O)
–t
(∅)
+t
(∅)
t
JIT(∅)
+t
SK(O)
t
SK(PP)
Max. skew
CCLK
Common
QFB
Device 1
Any Q
Device 1
QFB
Device2
Any Q
Device 2
