Advanced Clock Drivers Device Data
Freescale Semiconductor 13
MPC9773
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9773 clock driver. For the series terminated
case, however, there is no DC current draw; thus the outputs
can drive multiple series terminated lines. Figure 12
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC9773 clock driver is
effectively doubled due to its capability to drive multiple lines.
Figure 12. Single versus Dual Transmission Lines
The waveform plots in Figure 13 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9773 output buffer
is more than sufficient to drive 50-Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations that a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9773. The output waveform
in Figure 13 shows a step in the waveform. This step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the
36-Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
V
L
=V
S
(Z
0
÷ (R
S
+ R
0
+ Z
0
))
Z
0
=50 Ω || 50 Ω
R
S
=36 Ω || 36 Ω
R
0
=14 Ω
V
L
= 3.0 (25 ÷ (18+17+25)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
1. Final skew data pending specification.
Figure 13. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 14 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Figure 14. Optimized Dual Line Termination
14 Ω
In
MPC9773
Output
Buffer
R
S
= 36 Ω
Z
O
= 50 Ω
OutA
14 Ω
In
MPC9773
Output
Buffer
R
S
= 36 Ω
Z
O
= 50 Ω
OutB0
R
S
= 36 Ω
Z
O
= 50 Ω
OutB1
Time (ns)
Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
14 Ω
MPC9773
Output
Buffer
R
S
= 22 Ω
Z
O
= 50 Ω
R
S
= 22 Ω
Z
O
= 50 Ω
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
