Advanced Clock Drivers Device Data
4 Freescale Semiconductor
MPC9773
Table 3. Output Divider Bank A (N
A
)
VCO_SEL FSEL_A1 FSEL_A0 QA[0:3]
0 0 0 VCO ÷ 8
0 0 1 VCO ÷ 12
0 1 0 VCO ÷ 16
0 1 1 VCO ÷ 24
1 0 0 VCO ÷ 4
1 0 1 VCO ÷ 6
1 1 0 VCO ÷ 8
1 1 1 VCO ÷ 12
Table 4. Output Divider Bank B (N
B
)
VCO_SEL FSEL_B1 FSEL_B0 QB[0:3]
0 0 0 VCO ÷ 8
0 0 1 VCO ÷ 12
0 1 0 VCO ÷ 16
0 1 1 VCO ÷ 20
1 0 0 VCO ÷ 4
1 0 1 VCO ÷ 6
1 1 0 VCO ÷ 8
1 1 1 VCO ÷ 10
Table 5. Ouput Divider Bank C (N
C
)
VCO_SEL FSEL_C1 FSEL_C0 QC[0:3]
0 0 0 VCO ÷ 4
0 0 1 VCO ÷ 8
0 1 0 VCO ÷ 12
0 1 1 VCO ÷ 16
1 0 0 VCO ÷ 2
1 0 1 VCO ÷ 4
1 1 0 VCO ÷ 6
1 1 1 VCO ÷ 8
Table 6. Output Divider PLL Feedback (M)
VCO_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB
0 0 0 0 VCO ÷ 8
0 0 0 1 VCO ÷ 12
0 0 1 0 VCO ÷ 16
0 0 1 1 VCO ÷ 20
0 1 0 0 VCO ÷ 16
0 1 0 1 VCO ÷ 24
0 1 1 0 VCO ÷ 32
0 1 1 1 VCO ÷ 40
1 0 0 0 VCO ÷ 4
1 0 0 1 VCO ÷ 6
1 0 1 0 VCO ÷ 8
1 0 1 1 VCO ÷ 10
1 1 0 0 VCO ÷ 8
1 1 0 1 VCO ÷ 12
1 1 1 0 VCO ÷ 16
1 1 1 1 VCO ÷ 20
Advanced Clock Drivers Device Data
Freescale Semiconductor 5
MPC9773
Table 7. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
÷ 2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch-Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 12 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 8. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage –0.3 3.9 V
V
IN
DC Input Voltage –0.3 V
CC
+ 0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+ 0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage Temperature –65 125 °C
Table 9. DC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= -40°C to 85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
CC_PLL
PLL Supply Voltage 3.0 V
CC
V LVCMOS
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
V
PP
Peak-to-Peak Input Voltage PCLK, PCLK 250 mV LVPECL
V
CMR
Common Mode Range
(1)
PCLK, PCLK
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
1.0 V
CC
– 0.6 V LVPECL
V
OH
Output High Voltage 2.4 V I
OH
= –24 mA
(2)
2. The MPC9773 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
I
OL
= 12 mA
Z
OUT
Output Impedance 14 – 17
I
IN
Input Current
(3)
3. Inputs have pull-down resistors affecting the input current.
±200 µA V
IN
= V
CC
or GND
I
CC_PLL
Maximum PLL Supply Current 8.0 13.5 mA V
CC_PLL
Pin
I
CCQ
Maximum Quiescent Supply Current 35 mA All V
CC
Pins
Advanced Clock Drivers Device Data
6 Freescale Semiconductor
MPC9773
Table 10. AC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= -40°C to 85°C)
(1),
(2)
Symbol Characteristics Min Typ Max Unit Condition
f
REF
Input Reference Frequency ÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
Input Reference Frequency in PLL Bypass Mode
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
15.1
12.1
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
f
VCO
VCO Frequency Range 200 485 MHz
f
MAX
Output Frequency ÷ 2 output
÷ 4 output
÷ 6 output
÷ 8 output
÷ 10 output
÷ 12 output
÷ 16 output
÷ 20 output
÷ 24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
242.5
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
f
STOP_CLK
Serial Interface Clock Frequency 20 MHz
V
PP
Peak-to-Peak Input Voltage PCLK, PCLK 400 1000 mV LVPECL
V
CMR
Common Mode Range
(3)
PCLK, PCLK 1.2 V
CC
– 0.9 V LVPECL
t
PW,MIN
Input Reference Pulse Width
(4)
2.0 ns
t
R
, t
F
CCLKx Input Rise/Fall Time
(5)
1.0 ns 0.8 to 2.0 V
t
()
Propagation Delay (static phase offset)
(6)
6.25 MHz < f
REF
< 65.0 MHz
65.0 MHz < f
REF
< 125 MHz
f
REF
= 50 MHz and feedback = ÷8
–3
–4
–166
+3
+4
+166
°
°
ps
PLL locked
t
SK(O)
Output-to-Output Skew
(7)
within QA outputs
within QB outputs
within QC outputs
all outputs
100
100
100
250
ps
ps
ps
ps
DC Output Duty Cycle
(8)
(T÷2) –200 T÷2 (T÷2) +200 ps
t
R
, t
F
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
t
PLZ, HZ
Output Disable Time 8.0 ns
t
PZL, LZ
Output Enable Time 8.0 ns
t
JIT(CC)
Cycle-to-cycle Jitter
(9)
150 ps
t
JIT(PER)
Period Jitter
(10)
100 ps
t
JIT()
I/O Phase Jitter RMS (1 σ)
(11)
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(VCO = 400 MHz)

MPC9773FA

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Phase Locked Loops - PLL 3.3V 240MHz Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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