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IS61WV51232BLL-10BLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.e
p
s
ADDRESS
OE
BWa-d
CE
D
OUT
t
HZCE
t
HZB
t
BA
t
LZB
READ CYCLE NO. 2
(1,3)
(CE and OE Controlled)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CE =
Vil.
3. Address is valid prior to or coincident with CELOWtransitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = Vil)
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(OverOperatingRange)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
twC WriteCycleTime 8 — 10 — ns
tsCe CEtoWriteEnd 6.5 — 8 — ns
taw AddressSetupTime 6.5 — 8 — ns
toWriteEnd
tha AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwb BWa-dValidtoEndofWrite 6.5 — 8 — ns
tPwe1 WE Pulse Width 6.5 — 8 — ns
tPwe2 WE Pulse Width (OE=LOW) 8.0 — 10 — ns
tsd DataSetuptoWriteEnd 5 — 6 — ns
thd DataHoldfromWriteEnd 0 — 0 — ns
thzwe
(2)
WELOWtoHigh-ZOutput — 3.5 — 5 ns
tlzwe
(2)
WEHIGHtoLow-ZOutput 2 — 2 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vand
outputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOW,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
anyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeof
the signal that terminates the write. Shaded area product in development
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/01/2016
IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
-20 ns
Symbol Parameter Min. Max. Unit
twC WriteCycleTime 20 — ns
tsCe CEtoWriteEnd 12 — ns
taw AddressSetupTime 12 — ns
toWriteEnd
tha AddressHoldfromWriteEnd 0 — ns
tsa AddressSetupTime 0 — ns
tPwb
BWa-d
ValidtoEndofWrite 12 — ns
tPwe1 WE Pulse Width (OE=HIGH) 12 — ns
tPwe2 WE Pulse Width (OE=LOW) 17 — ns
tsd DataSetuptoWriteEnd 9 — ns
thd DataHoldfromWriteEnd 0 — ns
thzwe
(3)
WELOWtoHigh-ZOutput — 9 ns
tlzwe
(3)
WEHIGHtoLow-ZOutput 3 — ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulselevelsof0Vto0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not
100% tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.Allsignalsmustbeinvalid
statestoinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupand
Holdtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IS61WV51232BLL-10BLI

Mfr. #:
Buy IS61WV51232BLL-10BLI
Manufacturer:
ISSI
Description:
SRAM 16M (512Kx32) 10ns Async SRAM 3.3v
Lifecycle:
New from this manufacturer.
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