LTC3858
13
3858fc
OPERATION
(Refer to the Functional Diagram)
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IR, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller is in discontinuous operation.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads
or under large transient conditions. The peak inductor
current is determined by the voltage on the I
TH
pin, just
as in normal operation. In this mode, the effi ciency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry. In
forced continuous mode, the output ripple is independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LTC3858 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference when compared to Burst Mode
operation. It provides higher light load effi ciency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3858’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV
CC
or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects 535kHz. Placing a resistor between FREQ and SGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 9
A phase-locked loop (PLL) is available on the LTC3858
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
phase detector adjusts the voltage (through an internal
lowpass fi lter) of the VCO input to align the turn-on of
controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller 2’s
external top MOSFET is 180 degrees out of phase to the
rising edge of the external clock source.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop fi lter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 1MHz, with a guarantee over all
manufacturing variations to be between 75kHz and 850kHz.
In other words, the LTC3858’s PLL is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling).
PolyPhase
®
Applications (CLKOUT and PHASMD Pins)
The LTC3858 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3858 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
