LTC3727A-1
19
3727a1fa
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb
the sense currents; however, R1 is still bounded by the
V
OSENSE
feedback current.
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins that
provide a soft-start function and a means to shut down the
LTC3727A-1. Soft-start reduces the input power source’s
surge currents by gradually increasing the controllers
current limit (proportional to V
ITH
). This pin can also be
used for power supply sequencing.
An internal 1.2μA current source charges up the C
SS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to
start operating. As the voltage on RUN/SS increases from
1.5V to 3.0V, the internal current limit is increased from
45mV/R
SENSE
to 135mV/R
SENSE
. The output current limit
ramps up slowly, taking an additional 1.25s/μF to reach full
current. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
t
V
μA
C s μF C
t
V
DELAY SS SS
IRAMP
==
()
=
15
12
125
3
.
.
./
115
12
125
.
.
./
V
μA
C s μF C
SS SS
=
()
By pulling both RUN/SS pins below 1V, the LTC3727A-1
is put into low current shutdown (I
Q
= 20μA). The RUN/
SS pins can be driven directly from logic as shown in
Figure 7. Diode D1 in Figure 7 reduces the start delay
but allows C
SS
to ramp up slowly providing the soft-start
function. Each RUN/SS pin has an internal 6V zener clamp
(See Functional Diagram).
Fault Conditions: Current Limit and Current Foldback
The LTC3727A-1 current comparator has a maximum
sense voltage of 135mV resulting in a maximum MOSFET
APPLICATIONS INFORMATION
current of 135mV/R
SENSE
. The maximum value of current
limit generally occurs with the largest V
IN
at the highest
ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3727A-1 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then
the maximum sense voltage is progressively lowered from
135mV to 45mV. Under short-circuit conditions with very
low duty cycles, the LTC3727A-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
ON(MIN)
of the LTC3727A-1 (less than 200ns), the input voltage
and inductor value:
ΔI
L(SC)
= t
ON(MIN)
(V
IN
/L)
The resulting short-circuit current is:
I
mV
R
I
SC
SENSE
LSC
=+
45 1
2
Δ
()
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to fl ow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
Figure 7
3.3V OR 5V RUN/SS
RUN/SS
D1
C
SS
C
SS
3727 F07
(7a) (7b)
LTC3727A-1
20
3727a1fa
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V
OUT
returns to a safe
level, normal operation automatically resumes. A shorted
top MOSFET will result in a high current condition which
will open the system fuse. The switching regulator will
regulate properly with a leaky top MOSFET by altering the
duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3727A-1 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the center
frequency f
O
. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 380kHz. The
nominal operating frequency range of the LTC3727A-1 is
250kHz to 550kHz.
The phase detector used is an edge sensitive digital
type which provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, Δf
H
, is equal to the capture range, Δf
C
:
Δf
H
= Δf
C
= ±0.5 f
O
(250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
lter network on the PLLFLTR pin.
APPLICATIONS INFORMATION
If the external frequency (f
PLLIN
) is greater than the
oscillator frequency f
OSC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than f
OSC
, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. Thus the voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the external and
internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor C
LP
holds the voltage. The LTC3727A-1 PLLIN
pin must be driven from a low impedance source such as
a logic gate located close to the pin. When using multiple
LTC3727A-1s for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
masters frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillators PLLFLTR pin is recommended
in order to meet this requirement. The resultant operating
frequency can range from 310kHz to 470kHz.
The loop fi lter components (C
LP
, R
LP
) smooth out the cur-
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The lter com-
ponents C
LP
and R
LP
determine how fast the loop acquires
lock. Typically R
LP
=10kΩ and C
LP
is 0.01μF to 0.1μF.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest time duration
that the LTC3727A-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
()
<
LTC3727A-1
21
3727a1fa
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3727A-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3727A-1 is approximately
120ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
170ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in
this situation, a signifi cant amount of cycle skipping can
occur with correspondingly larger inductor current and
output voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current fl ows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the V
IN
/V
OUT
ratio is low, the synchronous switch may not be on for a
suffi cient amount of time to transfer power from the output
capacitor to the secondary load. Forced continuous opera-
tion will support secondary windings providing there is
suffi cient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
The secondary output voltage V
SEC
is normally set as shown
in Figure 6 by the turns ratio N of the transformer:
V
SEC
(N + 1) V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≅+
08 1
6
5
APPLICATIONS INFORMATION
where R5 and R6 are shown in Figure 2.
If V
SEC
drops below this level, the FCB voltage forces
temporary continuous switching operation until V
SEC
is
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18mA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB PIN CONDITION
0V to 0.75V Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
0.85V < VFCB < 6.8V Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors Regulating a Secondary Winding
>7.3V Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifi cations. Voltage positioning can easily be added
to the LTC3727A-1 by loading the I
TH
pin with a resistive
divider having a Thevenin equivalent voltage source
equal to the midpoint operating voltage range of the error
amplifi er, or 1.2V (see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifi er.
The maximum output voltage deviation can theoretically
be reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10
(see www.linear.com).

LTC3727AIG-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, 2-Phase Synchronous Controller w/ up to 14V Output
Lifecycle:
New from this manufacturer.
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