LTC3727A-1
8
3727a1fa
PIN FUNCTIONS
RUN/SS1, RUN/SS2 (Pins 1, 15): Combination of
Soft-Start, Run Control Inputs. A capacitor to ground at
each of these pins sets the ramp time to full output current.
Forcing either of these pins back below 1.0V causes the
IC to shut down the circuitry required for that particular
controller.
SENSE1
+
, SENSE2
+
(Pins 2, 14): The (+) Input to the
Differential Current Comparators. The I
TH
pin voltage and
controlled offsets between the SENSE
–
and SENSE
+
pins in
conjunction with R
SENSE
set the current trip threshold.
SENSE1
–
, SENSE2
–
(Pins 3, 13): The (–) Input to the
Differential Current Comparators.
V
OSENSE1
, V
OSENSE2
(Pins 4, 12): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5): The phase-locked loop’s lowpass fi lter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
100kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding. Pulling this pin below 0.8V will
force continuous synchronous operation. Do not leave
this pin fl oating.
I
TH1
, I
TH2
(Pins 8, 11): Error Amplifi er Outputs and
Switching Regulator Compensation Points. Each associ-
ated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9): Small Signal Ground. Common to
both controllers; must be routed separately from high
current grounds to the common (–) terminals of the
C
OUT
capacitors.
3.3V
OUT
(Pin 10): Linear Regulator Output. Capable of
supplying 10mA DC with peak currents as high as
50mA.
PGND (Pin 20): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifi ers and the (–) terminal(s)
of C
IN
.
INTV
CC
(Pin 21): Output of the Internal 7.5V Linear Low
Dropout Regulator and the EXTV
CC
Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7μF
tantalum or other low ESR capacitor.
EXTV
CC
(Pin 22): External Power Input to an Internal
Switch Connected to INTV
CC
. This switch closes and
supplies V
CC
power, bypassing the internal low dropout
regulator, whenever EXTV
CC
is higher than 7.3V. See
EXTV
CC
connection in Applications section. Do not exceed
8.5V on this pin.
BG1, BG2 (Pins 23, 19): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage swing
at these pins is from ground to INTV
CC
.
V
IN
(Pin 24): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes are
tied between the boost and INTV
CC
pins. Voltage swing at
the boost pins is from INTV
CC
to (V
IN
+ INTV
CC
).
SW1, SW2 (Pins 26, 17): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V
IN
.
TG1, TG2 (Pins 27, 16): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of
fl oating drivers with a voltage swing equal to INTV
CC
– 0.5V
superimposed on the switch node voltage SW.
PGOOD (Pin 28): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on either V
OSENSE
pin
is not within ±7.5% of its set point.
