1
®
ISL12024
Real-Time Clock/Calendar with Embedded
Unique ID
The ISL12024 device is a micro-power real-time clock with
embedded 64-bit unique ID, timing and crystal
compensation, clock/calender, power-fail indicator, two
periodic or polled alarms, intelligent battery backup
switching, and integrated 512x8-bit EEPROM configured in
16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Pinouts
ISL12024
(8 LD SOIC)
TOP VIEW
ISL12024
(8 LD TSSOP)
TOP VIEW
Features
Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
64-bit Unique ID
Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
Automatic Backup to Battery or Super Cap
On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
512x8-Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of BlockLock™
Protection
- Single Byte Write Capability
High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
•I
2
C Bus™
- 400kHz Data Transfer Rate
800nA Battery Supply Current
Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
- Pin-Compatible with the ISL12026
Pb-Free (RoHS Compliant)
Applications
Utility Meters
Audio Video Equipment
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Computer Products
Security Related Application
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
V
DD
RANGE
TEMP
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL12024IBZ* 12024 IBZ 2.7V to
5.5V
-40 to +85 8 Ld SOIC M8.15
ISL12024IVZ* 2024 IVZ 2.7V to
5.5V
-40 to +85 8 Ld TSSOP M8.173
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
X1
X2
V
BAT
V
DD
IRQ/F
OUT
SCL
SDA
GND
1
2
3
4
7
8
6
5
X1
X2
V
BAT
V
DD
IRQ/F
OUT
SCL
SDA
GND
1
2
3
4
7
8
6
5
Data Sheet FN6370.3August 18, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
I
2
C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2006, 2007, 2008.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
2
FN6370.3
August 18, 2008
Block Diagram
X1
X2
OSCILLATOR
FREQUENCY
TIMER
LOGIC
DIVIDER
CALENDAR
8
CONTROL/
REGISTERS
1Hz
TIME
KEEPING
REGISTERS
ALARM REGS
COMPARE
MASK
CONTROL
DECODE
LOGIC
ALARM
(EEPROM)
(EEPROM)
SCL
SDA
SERIAL
INTERFACE
DECODER
4k
EEPROM
ARRAY
REGISTERS
STATUS
(SRAM)
SELECT
IRQ/F
OUT
V
DD
V
BAT
32.768kHz
(SRAM)
BATTERY
CIRCUITRY
SWITCH
OSC
COMPENSATION
Pin Descriptions
PIN NUMBER
SYMBOL DESCRIPTIONSOIC TSSOP
1 3 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. (See “Application Section
on page 20.)
2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. (See “Application Section” on page 20.)
35IRQ/
F
OUT
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency
output pin. The function is set via the control register. This output is an open drain configuration.
4 6 GND Ground.
5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
71V
BAT
This input provides a backup supply voltage to the device. V
BAT
supplies power to the device in the event
that the V
DD
supply fails. This pin should be tied to ground if not used.
82V
DD
Power Supply.
ISL12024
3
FN6370.3
August 18, 2008
Absolute Maximum Ratings Thermal Information
Voltage on V
DD
, V
BAT
, SCL, SDA, and IRQ/F
OUT
Pins
(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±2kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Resistance (Typical, Note 2) θ
JA
°C/W
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 120
8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . 140
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
2. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Operating Specifications Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are @ T
A
= +25°C and
V
DD
= 3.3V.
SYMBOL PARAMETER CONDITIONS
MIN
(Note 12) TYP
MAX
(Note 12) UNIT
V
DD
Main Power Supply 2.7 5.5 V
V
BAT
Backup Power Supply 1.8 5.5 V
Electrical Specifications
SYMBOL PARAMETER CONDITIONS
MIN
(Note 12) TYP
MAX
(Note 12) UNIT NOTES
I
DD1
Supply Current with I
2
C Active V
DD
= 2.7V 500 µA 3, 4, 5
V
DD
= 5.5V 800 µA
I
DD2
Supply Current for Non-Volatile
Programming
V
DD
= 2.7V 2.5 mA 3, 4, 5
V
DD
= 5.5V 3.5 mA
I
DD3
Supply Current for Main
Timekeeping (Low Power Mode)
V
DD
= V
SDA
= V
SCL
= 2.7V 10 µA 5
V
DD
= V
SDA
= V
SCL
= 5.5V 20 µA 5
I
BAT
Battery Supply Current V
BAT
= 1.8V, V
DD
= V
SDA
= V
SCL
=
0V
800 1000 nA 3, 6, 7
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= 0V
850 1200 nA 3, 6, 7
I
BATLKG
Battery Input Leakage V
DD
= 5.5V, V
BAT
= 1.8V 100 nA
V
TRIP
V
BAT
Mode Threshold 1.8 2.2 2.6 V 7
V
TRIPHYS
V
TRIP
Hysteresis 30 mV 7,10
V
BATHYS
V
BAT
Hysteresis 50 mV 7,10
V
DD SR-
V
DD
Negative Slew Rate 10 V/ms 8
IRQ
/F
OUT
V
OL
Output Low Voltage V
DD
= 5V
I
OL
= 3mA
0.4 V
V
DD
= 1.8V
I
OL
= 1mA
0.4 V
I
LO
Output Leakage Current V
DD
= 5.5V
V
OUT
= 5.5V
100 400 nA
ISL12024

ISL12024IVZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLK/CLNDR W/EEPROM IN 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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