22
FN6370.3
August 18, 2008
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/
F
OUT
output
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
Once the registers are set, the following waveform will be
seen at IRQ/
F
OUT
:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
I
2
C Communications During Battery Backup
Operation in Battery Backup Mode is affected by the BSW
and SBIB bits as described earlier. These bits allow flexible
operation of the serial bus and EEPROM in Battery Backup
Mode, but certain operational details need to be clear before
utilizing the different modes. Table 8 describes four different
modes possible with using the BSW and SBIB bits, and how
they affect the serial interface and battery backup operation.
• Mode A - In this mode, selection bits indicate a Standard
Mode switchover combined with I
2
C operation in Battery
Backup Mode. When the V
DD
voltage drops below the
lower of V
TRIP
or V
BAT
, then the device will enter Battery
Backup Mode. If the microcontroller and bus pull-ups are
also powered by the battery, then the ISL12024 can
communicate in Battery Backup Mode.
• Mode B - In this mode selection, bits indicate Legacy
Mode switchover combined with I
2
C operation in Battery
Backup Mode. When the V
DD
voltage drops below V
BAT
,
the device will enter Battery Backup Mode. If the
microcontroller and bus pull-ups are also powered by the
battery, then the ISL12024 can communicate in Battery
Backup Mode. This mode places the ISL12024 device in
the same operating mode as the X1226 legacy device.
• Mode C - This mode combines Standard Mode battery
switchover with no I
2
C operation in Battery Backup Mode.
When the V
DD
voltage drops below the lower of V
TRIP
or
ALARM0
REGISTER
BIT
DESCRIPTION76543210HEX
SCA0 00000000 00hSeconds disabled
MNA0 10110000B0hMinutes set to 30,
enabled
HRA0 10010001 91hHours set to 11,
enabled
DTA0 10000001 81hDate set to 1,
enabled
MOA0 10000001 81hMonth set to 1,
enabled
DWA0 00000000 00hDay of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 00100000 x0hEnable Alarm
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
V
DD
V
BAT
V
SS
SUPER CAP
2.7V TO 5.5V
ALARM0
REGISTER
BIT
DESCRIPTION76543210HEX
SCA0 10110000B0hSeconds set to 30,
enabled
MNA0 0000000000hMinutes disabled
HRA0 0000000000hHours disabled
DTA0 0000000000hDate disabled
MOA0 0000000000hMonth disabled
DWA0 0000000000hDay of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 10100000x0hEnable Alarm and Int
Mode
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
ISL12024
