ISL12024IVZ-T Datasheet ISL12024IBZ, ISL12024IBZ-T, ISL12024IVZ | P19-P21

FN6370.3

August 18, 2008

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a stop condition during the

ninth cycle or hold SDA HIGH during the ninth clock cycle

and then issue a stop condition.

Random Read

Random read operations allow the master to access any

location in the ISL12024. Prior to issuing the Slave Address

Byte with the R/W

bit set to zero, the master must first

perform a “dummy” write operation.

The master issues the start condition and the slave address

byte, receives an acknowledge, then issues the word

address bytes. After acknowledging receipt of each word

address byte, the master immediately issues another start

condition and the slave address byte with the R/W

bit set to

one. This is followed by an acknowledge from the device and

then by the 8-bit data word. The master terminates the read

operation by not responding with an acknowledge and then

issuing a stop condition. See Figure 21 for the address,

acknowledge and data transfer sequence.

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of the

second start shown in Figure 21. The ISL12024 then goes

into Standby Power Mode after the stop and all bus activity

will be ignored until a start is detected. This operation loads

the new address into the address counter. The next Current

Address Read operation will read from the newly loaded

address. This operation could be useful if the master knows

the next address it needs to read, but is not ready for the

data.

Sequential Read

Sequential reads can be initiated as either a current address

read or random address read. The first data byte is

transmitted as with the other modes; however, the master

now responds with an acknowledge, indicating it requires

additional data. The device continues to output data for each

acknowledge received. The master terminates the read

operation by not responding with an acknowledge and then

issuing a stop condition.

The data output is sequential, with the data from address n

followed by the data from address n + 1. The address

counter for read operations increments through all page and

column addresses, allowing the entire memory contents to

be serially read during one operation. At the end of the

address space the counter “rolls over” to the start of the

address space and the ISL12024 continues to output data

for each acknowledge received. See Figure 22 for the

acknowledge and data transfer sequence.

SLAVE

ADDRESS

WORD

ADDRESS 1

SLAVE

ADDRESS

DATA

SDA BUS

SIGNALS FROM

THE SLAVE

SIGNALS FROM

THE MASTER

WORD

ADDRESS 0

1111

0000000

FIGURE 21. RANDOM ADDRESS READ SEQUENCE

DATA

(2)

SLAVE

ADDRESS

DATA

(n)

SDA BUS

SIGNALS FROM

THE SLAVE

SIGNALS FROM

THE MASTER

DATA

(n-1)

(n is any integer greater than 1)

DATA

(1)

FIGURE 22. SEQUENTIAL READ SEQUENCE

ISL12024

FN6370.3

August 18, 2008

Application Section

Crystal Oscillator and Temperature Compensation

Intersil has now integrated the oscillator compensation

circuity on-chip, to eliminate the need for external

components and adjust for crystal drift over-temperature and

enable very high accuracy time keeping (<5ppm drift).

The Intersil RTC family uses an oscillator circuit with on-chip

crystal compensation network, including adjustable

load-capacitance. The only external component required is

the crystal. The compensation network is optimized for

operation with certain crystal parameters which are common

in many of the surface mount or tuning-fork crystals available

today. Table 6 summarizes these parameters.

Table 7 contains some crystal manufacturers and part

numbers that meet the requirements for the Intersil RTC

products.

The turnover-temperature in Table 6 describes the

temperature where the apex of the of the drift vs temperature

curve occurs. This curve is parabolic with the drift increasing

as (T-T0)

. For an Epson MC-405 device, for example, the

turnover-temperature is typically +25°C, and a peak drift of

>110ppm occurs at the temperature extremes of -40 and

+85°C. It is possible to address this variable drift by adjusting

the load capacitance of the crystal, which will result in

predictable change to the crystal frequency. The Intersil RTC

family allows this adjustment over-temperature since the

devices include on-chip load capacitor trimming. This control

is handled by the Analog Trimming Register, or ATR, which

has 6-bits of control. The load capacitance range covered by

the ATR circuit is approximately 3.25pF to 18.75pF, in

0.25pF increments. Note that actual capacitance would also

include about 2pF of package related capacitance. In-circuit

tests with commercially available crystals demonstrate that

this range of capacitance allows frequency control from

+80ppm to -34ppm, using a 12.5pF load crystal.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature

is available for the Intersil RTC family. There are 3-bits

known as the Digital Trimming Register or DTR, and they

operate by adding or skipping pulses in the clock signal. The

range provided is ±30ppm in increments of 10ppm. The

default setting is 0ppm. The DTR control can be used for

coarse adjustments of frequency drift over-temperature or

for crystal initial accuracy correction.

A final application for the ATR control is in-circuit calibration

for high accuracy applications, along with a temperature

sensor chip. Once the RTC circuit is powered up with battery

backup, the IRQ

OUT

output is set at 32.768kHz and

frequency drift is measured. The ATR control is then

adjusted to a setting which minimizes drift. Once adjusted at

a particular temperature, it is possible to adjust at other

discrete temperatures for minimal overall drift, and store the

resulting settings in the EEPROM. Extremely low overall

temperature drift is possible with this method. The Intersil

evaluation board contains the circuitry necessary to

implement this control.

TABLE 6. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs

PARAMETER MIN TYP MAX UNITS NOTES

Frequency 32.768 kHz

Frequency Tolerance ±100 ppm Down to 20ppm if desired

Turnover Temperature 20 25 30 °C Typically the value used for most crystals

Operating Temperature Range -40 85 °C

Parallel Load Capacitance 12.5 pF

Equivalent Series Resistance 50 k

Ω For best oscillator performance

TABLE 7. CRYSTAL MANUFACTURERS

MANUFACTURER PART NUMBER TEMP RANGE (°C) +25°C FREQUENCY TOLERANCE (PPM)

Citizen CM201, CM202, CM200S -40 to +85 ±20

Epson MC-405, MC-406 -40 to +85 ±20

Raltron RSM-200S-A or B -40 to +85 ±20

SaRonix 32S12A or B -40 to +85 ±20

Ecliptek ECPSM29T-32.768K -10 to +60 ±20

ECS ECX-306/ECX-306I -10 to +60 ±20

Fox FSM-327 -40 to +85 ±20

ISL12024

FN6370.3

August 18, 2008

Layout Considerations

The crystal input at X1 has a very high impedance and will

pick up high frequency signals from other circuits on the

board. Since the X2 pin is tied to the other side of the crystal,

it is also a sensitive node. These signals can couple into the

oscillator circuit and produce double clocking or

mis-clocking, seriously affecting the accuracy of the RTC.

Care needs to be taken in layout of the RTC circuit to avoid

noise pickup. Figure 23 is a suggested layout for the

ISL12024 or ISL12026 devices in an 8 Ld SO package.

The X1 and X2 connections to the crystal are to be kept as

short as possible. A thick ground trace around the crystal is

advised to minimize noise intrusion, but ground near the X1

and X2 pins should be avoided as it will add to the load

capacitance at those pins. Keep in mind these guidelines for

other PCB layers in the vicinity of the RTC device. A small

decoupling capacitor at the V

pin of the chip is mandatory,

with a solid connection to ground.

The ISL12024 product has a special consideration. The

IRQ

OUT

pin on the 8 Ld SOIC package is located next to

the X2 pin. When this pin is used as a frequency output

(IRQ

OUT

) and is set to 32.768kHz, noise can couple to the

X1 or X2 pins and cause double-clocking. The layout in

Figure 23 minimizes this by running the IRQ

OUT

output

away from the X1 and X2 pins. Also, reducing the switching

current at this pin by careful selection of the pull-up resistor

value will reduce noise. Intersil suggests a minimum value of

5.1kΩ for 32.768kHz, and higher values (up to 20kΩ) for

lower frequency IRQ

OUT

outputs.

For other RTC products, the same rules previously stated

should be observed, but adjusted slightly since the packages

and pinouts are different.

Oscillator Measurements

When a proper crystal is selected and the layout guidelines

above are observed, the oscillator should start-up in most

circuits in less than one second. Some circuits may take

slightly longer, but startup should definitely occur in less than

5 seconds. When testing RTC circuits, the most common

impulse is to apply a scope probe to the circuit at the X2 pin

(oscillator output) and observe the waveform. DO NOT DO

THIS! Although in some cases you may see a useable

waveform, due to the parasitics (usually 10pF to ground)

applied with the scope probe, there will be no useful

information in that waveform other than the fact that the

circuit is oscillating. The X2 output is sensitive to capacitive

impedance so the voltage levels and the frequency will be

affected by the parasitic elements in the scope probe.

Applying a scope probe can possibly cause a faulty oscillator

to start-up, hiding other issues (although in the Intersil RTCs,

the internal circuitry assures start-up when using the proper

crystal and layout).

The best way to analyze the RTC circuit is to power it up and

read the real-time clock as time advances, or if the chip has

the IRQ

OUT

output, look at the output of that pin on an

oscilloscope (after enabling it with the control register, and

using a pull-up resistor for an open-drain output).

Alternatively, the ISL12024 device has an IRQ

OUT

output

which can be checked by setting an alarm for each minute.

Using the pulse interrupt mode setting, the once-per-minute

interrupt functions as an indication of proper oscillation.

Backup Battery Operation

Many types of batteries can be used with the Intersil RTC

products. 3.0V or 3.6V Lithium batteries are appropriate, and

sizes are available that can power a Intersil RTC device for

up to 10 years. Another option is to use a supercapacitor for

applications where V

may disappear intermittently for

short periods of time. Depending on the value of the Super

Cap used, backup time can last from a few days to two

weeks (with >1F). A simple silicon or Schottky barrier diode

can be used in series with V

to charge the Super Cap,

which is connected to the V

BAT

pin. Try to use Schottky

diodes with very low leakages, <1

µA desirable. Do not use

the diode to charge a battery (especially lithium batteries!)

There are two possible modes for battery backup operation;

Standard and Legacy Mode. In Standard Mode, there are no

operational concerns when switching over to battery backup

since all other devices functions are disabled. Battery drain

is minimal in Standard Mode, and return to Normal V

powered operations is predictable. In Legacy Mode, the

BAT

pin can power the chip if the voltage is above V

and

less than V

TRIP

. In this mode, it is possible to generate alarm

and communicate with the device, unless SBI = 1, but the

supply current drain is much higher than the Standard Mode

and backup time is reduced. In this case if alarms are used

in backup mode, the IRQ

OUT

pull-up resistor must be

connected to V

BAT

voltage source. During initial power-up

the default mode is the Standard Mode.

FIGURE 23. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8

47k

ISL12024

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ISL12024IVZ-T

Mfr. #:

Buy ISL12024IVZ-T

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock REAL TIME CLK/CLNDR W/EEPROM IN 8LD

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ISL12024IVZ-T

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