NB4N441
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10
Jitter Performance
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its
ideal position.
CycletoCycle Jitter (shortterm) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.
Figure 8. CycletoCycle Jitter
T
JITTER(cyclecycle)
= T
1
T
0
T
0
T
1
PeaktoPeak Jitter is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.
Figure 9. PeaktoPeak Jitter
Time
Typical
Gaussian
Distribution
RMS
or one
Sigma
Jitter
Jitter Amplitude
PeaktoPeak Jitter (8 s)
There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in periodtoperiod
or cycletocycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peaktopeak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
postprocessing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDSseries oscilloscopes have superb jitter
analysis capabilities on noncontiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from singleshot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
LongTerm Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is
10,000 observed cycles.
The NBC4N441 exhibit long term and cycletocycle
jitter, which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility associated
with a synthesizer over a fixed frequency oscillator. The
jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
NB4N441
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11
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
ORDERING INFORMATION
Device Package Shipping
NB4N441MNG QFN24
(PbFree)
92 Units / Rail
NB4N441MNR2G QFN24
(PbFree)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB4N441
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12
PACKAGE DIMENSIONS
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
SEATING
PLANE
D
B
0.15 C
A2
A
A3
A
E
PIN 1
IDENTIFICATION
2X
0.15 C
2X
0.08 C
0.10 C
A1
C
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A2 0.60 0.80
A3 0.20 REF
b 0.23 0.28
D 4.00 BSC
D2 2.70 2.90
E 4.00 BSC
E2 2.70 2.90
e 0.50 BSC
L 0.35 0.45
24X
L
D2
b
1
6
7
18
13
19
e
12
E2
e
24
0.10 B
0.05
AC
C
REF
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NBN441/D
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NB4N441MNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL MLTPRTCL PLL CLK SYN
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New from this manufacturer.
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