NB4N441
http://onsemi.com
7
APPLICATIONS INFORMATION
General
The NB4N441 is a precision clock synthesizer which
generates a differential LVPECL clock output frequency
from 12.5 MHz to 425 MHz. A three−wire SPI interface is
used to configure the device to produce the exact frequency
of one of sixteen predefined popular standard protocol
output frequencies from a single 27 MHz crystal reference;
see Table 1. This serial interface gives the user complete
control of each internal counter/divider.
If a different or custom output frequency is required, the
SPI interface can also enable the user to configure the device
for frequencies not specified in Table 1.
Input Clock / Crystal Functionality
To generate the exact protocol frequencies in Table 1, a
27.000 MHz frequency source is required. This can be
accomplished by connecting a 27.000 MHz crystal across
the XTAL1 and XTAL2 pins. If driving single ended, use the
XTAL1 pin and leave XTAL2 floating. The CLK/XTAL1
input will accept a LVTTL/LVCMOS input.
Frequency Control Logic Configuration
The NB4N441 includes a 5−bit input prescaler, a 10−bit
divider for the PLL feedback path and a 3−bit Output
Divider, which divides the VCO frequency by 2, 4, 8, 16, or
32. The Frequency Control Logic for the NB4N441
configures these dividers and counters through the
Serial inputs and will select one of the sixteen
predetermined clock frequencies in Table 1. The serial
interface can also be used to configure the device for user
specified custom frequencies not specified in Table 1.
Output frequencies are generated based on the following
equation: F
OUT
= (F
xtal
/P) * M B N, with the stipulation
that the internal VCO frequency be
400 MHz < VCO < 850 MHz with VCO = F
OUT
* N and
10 MHz < F
xtal
< 28 MHz.
Output Enable
The NB4N441 incorporates a synchronous output
Disable/Enable pin, OE. The synchronous output enable pin
insures no runt clock pulses are generated. When disabled,
CLKOUT is set LOW and CLKOUT
is set HIGH.
Table 8. Table 8. Output Enable Function
OE Function
1 Clock Outputs Enabled
0 Clock Outputs Disabled
CLKOUT = L, CLKOUT
= H
Lock Detect Functionality
The NB4N441 features a PLL Lock Detect function
which indicates the locked status of the PLL. When the PLL
is locked, the LOCKED
output pin asserts a logic Low.
When the internal phase lock is lost (such as when the input
clock stops, drifts beyond the pullable range of the crystal,
or suddenly shifts in phase), the LOCKED
output goes High.
Table 9. Table 9. Lock Detect Function
LOCKED Function
0 PLL is Locked
1 PLL is not Locked
Using the On−Board Crystal Oscillator
The NB4N441 features a fully integrated on−board
crystal oscillator to minimize system implementation costs.
The crystal should be fundamental mode, parallel
resonant. For exact tuning of cyrstal frequency, capacitors
should be connected from pins X1 and X2. Typical loading
should be on the order of 20 pF to 30 pF (on each crystal
input pin). As the oscillator is somewhat sensitive to loading
on its inputs, the user is advised to mount the crystal as close
to the NB4N441 as possible to avoid any board level
parasitic effects. To facilitate collocation, surface mount
crystals are recommended, but not required.
Table 10. CRYSTAL SPECIFICATIONS
Parameter Value
Crystal Cut Fundamental AT Cut
Resonance Parallel Resonance
Load Capacitance 18 pF
Frequency Tolerance ±15 ppm at 25°C
Frequency/Temperature Stability ±20 ppm 0 to 70°C
Operating Range 0 to 70°C or
−40 to +85°C
Shunt Capacitance 5 pF Max
Equivalent Series Resistance (ESR)
50 W Max
Correlation Drive Level
1.0 mW Max
Aging 5 ppm / Yr
(First 3 Years)
15 ppm /10 Yrs
