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AD8310ARMZ

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AD8310
Rev. F | Page 9 of 24
THEORY OF OPERATION
(
)
O
IN
SLOPE
OUT
PPVV −
=
Logarithmic amplifiers perform a more complex operation than
classical linear amplifiers, and their circuitry is significantly
different. A good grasp of what log amps do and how they do it
can help users avoid many pitfalls in their applications. For a
complete discussion of the theory, see the AD8307 data sheet.
The essential purpose of a log amp is not to amplify (though
amplification is needed internally), but to compress a signal of
wide dynamic range to its decibel equivalent. It is, therefore, a
measurement device. An even better term might be logarithmic
converter, because the function is to convert a signal from one
domain of representation to another via a precise nonlinear
transformation:
⎟
⎟
⎠
⎜
⎜
⎝
=
X
Y
OUT
V
VV log
⎞⎛
IN
V
(1)
where:
V
OUT
is the output voltage.
V
Y
is the slope voltage. The logarithm is usually taken to
base ten, in which case
V
Y
is also the volts-per-decade.
V
IN
is the input voltage.
V
X
is the intercept voltage.
Log amps implicitly require two references (here V
X
and V
Y
)
that determine the scaling of the circuit. The accuracy of a log
amp cannot be any better than the accuracy of its scaling
references. In the AD8310, these are provided by a band gap
reference.
V
OUT
5V
Y
4V
Y
3V
Y
2V
Y
V
Y
–2V
Y
V
OUT
=0
LOG V
IN
V
SHIFT
LOWER INTERCEPT
V
IN
=10
–2
V
X
–40dBc
V
IN
=10
2
V
X
+40dBc
V
IN
=10
4
V
X
+80dBc
V
IN
=V
X
0dBc
01084-021
Figure 21. General Form of the Logarithmic Function
While Equation 1, plotted in Figure 21, is fundamentally
correct, a different formula is appropriate for specifying the
calibration attributes or demodulating log amps like the
AD8310, operating in RF applications with a sine wave input.
(2)
where:
V
OUT
is the demodulated and filtered baseband (video or RSSI)
output.
V
SLOPE
is the logarithmic slope, now expressed in V/dB
(25 mV/dB for the AD8310).
P
IN
is the input power, expressed in dB relative to some
reference power level.
P
O
is the logarithmic intercept, expressed in dB relative to the
same reference level.
A widely used reference in RF systems is dB above 1 mW in
50 Ω, a level of 0 dBm. Note that the quantity (P
IN
− P
O
) is dB.
The logarithmic function disappears from the formula, because
the conversion has already been implicitly performed in stating
the input in decibels. This is strictly a concession to popular
convention. Log amps manifestly do not respond to power
(tacitly, power absorbed at the input), but rather to input
voltage. The input is specified in dBV (decibels with respect to
1 V rms) throughout this data sheet. This is more precise,
although still incomplete, because the signal waveform is also
involved. Many users specify RF signals in terms of power
(usually in dBm/50 Ω), and this convention is used in this data
sheet when specifying the performance of the AD8310.
PROGRESSIVE COMPRESSION
High speed, high dynamic-range log amps use a cascade of
nonlinear amplifier cells to generate the logarithmic function
as a series of contiguous segments, a type of piecewise linear
technique. The AD8310 employs six cells in its main signal
path, each having a small-signal gain of 14.3 dB (×5.2) and a
−3 dB bandwidth of about 900 MHz. The overall gain is about
20,000 (86 dB), and the overall bandwidth of the chain is
approximately 500 MHz, resulting in a gain-bandwidth product
(GBW) of 10,000 GHz, about a million times that of a typical
op amp. This very high GBW is essential to accurate operation
under small-signal conditions and at high frequencies. The
AD8310 exhibits a logarithmic response down to inputs as
small as 40 μV at 440 MHz.
Progressive compression log amps either provide a baseband
video response or accept an RF input and demodulate this
signal to develop an output that is essentially the envelope of the
input represented on a logarithmic or decibel scale. The
AD8310 is the latter kind. Demodulation is performed in a total
of nine detector cells. Six are associated with the amplifier
stages, and three are passive detectors that receive a progres-
sively attenuated fraction of the full input. The maximum signal
frequency can be 440 MHz, but, because all the gain stages are
dc-coupled, operation at very low frequencies is possible.
AD8310
Rev. F | Page 10 of 24
SLOPE AND INTERCEPT CALIBRATION
All monolithic log amps from Analog Devices use precision
design techniques to control the logarithmic slope and
intercept. The primary source of this calibration is a pair of
accurate voltage references that provide supply- and
temperature-independent scaling. The slope is set to 24 mV/dB
by the bias chosen for the detector cells and the subsequent gain
of the postdetector output interface. With this slope, the full
95 dB dynamic range can be easily accommodated within the
output swing capacity, when operating from a 2.7 V supply.
Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has
likewise been chosen to provide an output centered in the
available voltage range.
Precise control of the slope and intercept results in a log amp
with stable scaling parameters, making it a true measurement
device as, for example, a calibrated received signal strength
indicator (RSSI). In this application, the input waveform is
invariably sinusoidal. The input level is correctly specified in
dBV. It can alternatively be stated as an equivalent power, in
dBm, but in this case, it is necessary to specify the impedance in
which this power is presumed to be measured. In RF practice, it
is common to assume a reference impedance of 50 Ω, in which
0 dBm (1 mW) corresponds to a sinusoidal amplitude of
316.2 mV (223.6 mV rms). However, the power metric is
correct only when the input impedance is lowered to 50 Ω,
either by a termination resistor added across INHI and INLO,
or by the use of a narrow-band matching network.
Note that log amps do not inherently respond to power, but to
the voltage applied to their input. The AD8310 presents a
nominal input impedance much higher than 50 Ω (typically
1 kΩ at low frequencies). A simple input matching network
can considerably improve the power sensitivity of this type of
log amp. This increases the voltage applied to the input and,
therefore, alters the intercept. For a 50 Ω reactive match, the
voltage gain is about 4.8, and the whole dynamic range moves
down by 13.6 dB. The effective intercept is a function of wave-
form. For example, a square-wave input reads 6 dB higher than
a sine wave of the same amplitude, and a Gaussian noise input
reads 0.5 dB higher than a sine wave of the same rms value.
OFFSET CONTROL
In a monolithic log amp, direct coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which typically have a chip area at least as large as
that of a basic gain cell, considerably increasing die size. Second,
the capacitor values predetermine the lowest frequency at which
the log amp can operate. For moderate values, this can be as
high as 30 MHz, limiting the application range. Third, the
parasitic back-plate capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a real signal. If it were as
high as 400 μV, it would be 18 dB larger than the smallest ac
signal (50 μV), potentially reducing the dynamic range by this
amount. This problem can be averted by using a global feedback
path from the last stage to the first, which corrects this offset in
a similar fashion to the dc negative feedback applied around an
op amp. The high frequency components of the feedback signal
must, of course, be removed to prevent a reduction of the HF
gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppres-
sion of HF feedback to allow operation above 1 MHz. The −3 dB
point in the high-pass response is at 2 MHz, but the usable range
extends well below this frequency. To further lower the frequency
range, an external capacitor can be added at OFLT (Pin 3). For
example, 300 pF lowers it by a factor of 10.
Operation at low audio frequencies requires a capacitor of about
1 μF. Note that this filter has no effect for input levels well above
the offset voltage, where the frequency range would extend
down to dc (for a signal applied directly to the input pins). The
dc offset can optionally be nulled by adjusting the voltage on
the OFLT pin (see the
Applications Information section).
AD8310
Rev. F | Page 11 of 24
PRODUCT OVERVIEW
The AD8310 has six main amplifier/limiter stages. These six
cells and their and associated
g
m
styled full-wave detectors
handle the lower two-thirds of the dynamic range. Three top-
end detectors, placed at 14.3 dB taps on a passive attenuator,
handle the upper third of the 95 dB range. The first amplifier
stage provides a low noise spectral density (1.28 nV/√Hz).
Biasing for these cells is provided by two references: one
determines their gain, and the other is a band gap circuit that
determines the logarithmic slope and stabilizes it against supply
and temperature variations. The AD8310 can be enabled or
disabled by a CMOS-compatible level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally
scaled 2 μA/dB. The output voltage is developed by applying
this current to a 3 kΩ load resistor followed by a high speed
gain-of-four buffer amplifier, resulting in a logarithmic slope of
24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered
voltage can be accessed at BFIN (Pin 6), allowing certain
functional modifications such as the addition of an external
postdemodulation filter capacitor and the alteration or
adjustment of slope and intercept.
+
–
VPOS
INHI
INLO
COMM
3
8mA
1.0k
Ω
BAND GAP REFERENCE
AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
NINE DETECTOR CELLS
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
2
2
μ
A
/dB
MIRROR
3k
Ω
3k
Ω
1k
Ω
COMM
COMM
ENBL
BFIN
VOUT
OFLT
ENABLE
BUFFER
INPUT
OUTPUT
OFFSET
FILTER
AD8310
SUPPLY
+INPUT
–INPUT
COMMON
COMM
33pF
01084-022
Figure 22. Main Features of the AD8310
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current, if the main signal path
exhibits an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor that can be
increased in value by an off-chip component at OFLT (Pin 3).
The resulting voltage is used to null the offset at the output of
the first stage. Because it does not involve the signal input
connections, whose ac-coupling capacitors otherwise introduce
a second pole into the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built on an advanced, dielectrically isolated,
complementary bipolar process. In the following interface
diagrams shown in Figure 23 to Figure 26, resistors labeled as
R are thin-film resistors that have a low temperature coefficient
of resistance (TCR) and high linearity under large-signal
conditions. Their absolute tolerance is typically within ±20%.
Similarly, capacitors labeled as C have a typical tolerance of
±15% and essentially zero temperature or voltage sensitivity.
Most interfaces have additional small junction capacitances
associated with them, due to active devices or ESD protection,
which might not be accurate or stable. Component numbering
in these interface diagrams is local.
ENABLE INTERFACE
The chip-enable interface is shown in Figure 23. The currents in
the diode-connected transistors control the turn-on and turn-off
states of the band gap reference and the bias generator. They are
a maximum of 100 μA when ENBL is taken to 5 V under worst-
case conditions. For voltages below 1 V, the AD8310 is disabled
and consumes a sleep current of less than 1 μA. When tied to the
supply or a voltage above 2 V, it is fully enabled. The internal
bias circuitry is very fast (typically <100 ns for either off or on).
In practice, however, the latency period before the log amp
exhibits its full dynamic range is more likely to be limited by
factors relating to the use of ac coupling at the input or the
s
ett
ling of the offset-control loop (see the following sections).
COMM
ENBL
40kΩ
TO BIAS
STAGES
AD8310
01084-023
2
7
Figure 23. Enable Interface
INPUT INTERFACE
Figure 24 shows the essentials of the input interface. C
P
and C
M
are parasitic capacitances, and C
D
is the differential input
capacitance, largely due to Q1 and Q2. In most applications,
both input pins are ac-coupled. The S switches close when
enable is asserted. When disabled, bias current I
E
is shut off and
the inputs float; therefore, the coupling capacitors remain
charged. If the log amp is disabled for long periods, small
leakage currents discharge these capacitors. Then, if they are
poorly matched, charging currents at power-up can generate a
transient input voltage that can block the lower reaches of the
dynamic range until it becomes much less than the signal.
A single-sided signal can be applied via a blocking capacitor to
either Pin 1 or Pin 8, with the other pin ac-coupled to ground.
Under these conditions, the largest input signal that can be
handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V
supply; a 5 dBV input (2.5 V amplitude) can be handled with a
5 V supply. When using a fully balanced drive, this maximum
input level is permissible for supply voltages as low as 2.7 V.
Above 10 MHz, this is easily achieved using an LC matching
network. Such a network, having an inductor at the input,
usefully eliminates the input transient noted above.
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AD8310ARMZ

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Manufacturer:
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Description:
Logarithmic Amplifiers V-Out DC to 440 MHz 95dB
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