AD8310
Rev. F | Page 18 of 24
OUTPUT FILTERING
LOWERING THE HIGH-PASS CORNER FREQUENCY
OF THE OFFSET COMPENSATION LOOP
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
BFIN pin be left unconnected and free of any stray capacitance.
In normal operation using an ac-coupled input signal, the
OFLT pin should be left unconnected. Input-referred dc offsets
of about 1.5 mV in the signal path are nulled via an internal
offset control loop. This loop has a high-pass −3 dB corner at
about 2 MHz. In low frequency ac-coupled applications, it is
necessary to lower this corner frequency to prevent input
signals from being misinterpreted as offsets. An external
capacitor on OFLT lowers the high-pass corner to arbitrarily
low frequencies (Figure 36). For example, by using a 1 μF
capacitor, the 3 dB corner is reduced to 60 Hz.
The nominal output video bandwidth of 25 MHz can be reduced
by connecting a ground-referenced capacitor (C
FILT
) to the BFIN
pin, as shown in Figure 35. This is generally done to reduce out-
put ripple (at twice the input frequency for a symmetric input
waveform such as sinusoidal signals).
+4
2μA/dB
3kΩ
V
OUT
BFIN
C
FILT
AD8310
C
FILT
= 1/(2π× 3kΩ× VIDEO BANDWIDTH) – 2.1pF
01084-035
()
C
OFLT
(SEE TEXT)
AD8310
OFLT
01084-036
()
Figure 35. Lowering the Postdemodulation Video Bandwidth
C
FILT
is selected using the following equation:
Figure 36. Lowering the High-Pass Corner Frequency
of the Offset Control Loop
pF1.2
k32
1
×Ω×π
=
idthVideoBandw
C
FILT
(11)
The corner frequency is set by the following equation:
The video bandwidth should typically be set at a frequency
equal to about one-tenth the minimum input frequency. This
ensures that the output ripple of the demodulated log output,
which is at twice the input frequency, is well filtered.
In many log amp applications, it might be necessary to lower
the corner frequency of the postdemodulation filtering to
achieve low output ripple while maintaining a rapid response
time to changes in signal level. An example of a 4-pole active
filter is shown in the AD8307 data sheet.
OFLT
CORNER
C
f
××π
=
26252
1
(12)
where C
OFLT
is the capacitor connected to OFLT.
AD8310
Rev. F | Page 19 of 24
APPLICATIONS INFORMATION
The AD8310 is highly versatile and easy to use. It needs only a
few external components, most of which can be immediately
accommodated using the simple connections shown in the
Using the AD8310 section.
A few examples of more specialized applications are provided
in the following sections. See the AD8307 data sheet for more
applications (note the slightly different pin configuration).
CABLE-DRIVING
For a supply voltage of 3 V or greater, the AD8310 can drive a
grounded 100 Ω load to 2.5 V. If reverse-termination is required
when driving a 50 Ω cable, it should be included in series with
the output, as shown in Figure 37. The slope at the load is then
12 mV/dB. In some cases, it might be permissible to operate the
cable without a termination at the far end, in which case the
slope is not lowered. Where a further increase in slope is
desirable, the scheme shown in Figure 34 can be used.
AD8310
VOUT
50Ω
50Ω
01084-037
Figure 37. Output Response of Cable-Driver Application
DC-COUPLED INPUT
It might occasionally be necessary to provide response to dc
inputs. Because the AD8310 is internally dc-coupled, there is no
reason why this cannot be done. However, its differential inputs
must be positioned at least 2 V above the COM potential for
proper biasing of the first stage. Usually, the source is a single-
sided ground-referenced signal, so level-shifting and a single-
ended-to-differential conversion must be provided to correctly
drive the AD8310’s inputs.
Figure 38 shows how a level-shift to midsupply (2.5 V in this
example) and a single-ended-to-differential conversion can be
accomplished using the AD8138 differential amplifier. The four
499 Ω resistors set up a gain of unity. An output common-mode
(or bias) voltage of 2.5 is achieved by applying 2.5 V from a supply-
referenced resistive divider to the V
OCM
pin of the AD8138. The
differential outputs of the AD8138 directly drive the 1.1 kΩ
input impedance of the AD8310.
5V
0.01 F
μ
SIGNAL
INPUT
AD8138
0.1μF
5V
499Ω
499Ω
499Ω
499Ω
10kΩ
0.1μF
5V
10kΩ
NC
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
1234
8765
V
OUT
5V
3.01kΩ1.87kΩ
50Ω
2.5V
NC = NO CONNECT
01084-038
Figure 38. DC-Coupled Log Amp
In this application the offset voltage of the AD8138 must be
trimmed. The internal offset compensation circuitry of the
AD8310 is disabled by applying a nominal voltage of ~1.9 V to
the OFLT pin, so the trim on the AD8138 is effectively trimming
the offsets of both devices. The trim is done by grounding the
circuits input and slightly varying the gain resistors on the
inverting input of the AD8138 (a 50 Ω potentiometer is used in
this example) until the voltage on the AD8310’s output reaches
a minimum.
After trimming, the lower end of the dynamic range is limited
by the broadband noise at the output of the AD8138, which is
approximately 425 μV p-p. A differential low-pass filter can be
added between the AD8138 and the AD8310 when the very fast
pulse response of the circuit is not required.
INPUT LEVEL (mV)
0.1
RSSI OUTPUT (V)
1
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
10 100 1000
2.3
2.5
2.7
01084-039
Figure 39. Transfer Function of DC-Coupled Log Amp Application
AD8310
Rev. F | Page 20 of 24
EVALUATION BOARD
An evaluation board is available that has been carefully laid out
and tested to demonstrate the specified high speed performance
of the AD8310. Figure 40 shows the schematic of the evaluation
board, which follows the basic connections schematic shown in
Figure 27.
Connectors INHI, INLO, and VOUT are of the SMA type.
Supply and ground are connected to the TP1 and TP2 vector
pins. The layout and silkscreen for the component side of the
board are shown in Figure 41 and Figure 42. Switches and
component settings for different setups are described in Table 6.
For ordering information, see the Ordering Guide.
01084-041
C2
0.01μF
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
123
4
8765
C4
0.01μF
C1
0.01μF
R3
52.3Ω
SW1
A
B
R4
0
Ω
R1
0
Ω
INHI
INLO
TP2
C7
OPEN
W1 W2
R6
0Ω
C6
OPEN
R7
OPEN
V
OUT
C5
OPEN
C3
OPEN
R5
0Ω
TP1
VPOS
R2
0Ω
01084-040
Figure 40. Evaluation Board Schematic
Figure 41. Layout of the Component Side of the Evaluation Board
01084-042
Figure 42. Component Side Silkscreen of the Evaluation Board

AD8310ARMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers V-Out DC to 440 MHz 95dB
Lifecycle:
New from this manufacturer.
Delivery:
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