13©2016 Integrated Device Technology, Inc Revision B April 20, 2016
843N571I Data Sheet
Parameter Measurement Information, continued
LVPECL Output Rise/Fall Time
LVPECL Output Duty Cycle/Pulse Width/Period
LVCMOS Output Duty Cycle/Pulse Width/Period
nQ[A:C]
Q[A:C]
nQ[A:C]
Q[A:C]
QD0,
QREF[0:5]
14©2016 Integrated Device Technology, Inc Revision B April 20, 2016
843N571I Data Sheet
Applications Information
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be accomplished
by removing R1 and making R2 50. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm
C1
0.1uF
3.3V
3.3V
Crystal Input Interface
XTA L_ I N
XTA L_ O U T
Crystal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
15©2016 Integrated Device Technology, Inc Revision B April 20, 2016
843N571I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 2. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA

843N571BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner FemtoClock NG Clock Synthesizer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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