6©2016 Integrated Device Technology, Inc Revision B April 20, 2016
843N571I Data Sheet
Table 4C. LVPECL DC Characteristics, V
CC
= 3.3V ± 0.3V, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 5. Crystal Characteristics
AC Electrical Characteristics
Table 6A. LVPECL AC Characteristics, V
CC
= 3.3V ± 0.3V, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
– 1.4 V
CC
– 0.8 V
V
OL
Output Low Voltage; NOTE 1 V
CC
– 2.0 V
CC
– 1.6 V
V
SWING
Peak-to-Peak Output Voltage
Swing
0.6 1.0 V
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
IN
Input Frequency 25 MHz
f
OUT
Output Frequency 100 156.25 MHz
tjit()
RMS Phase Jitter (Random)
NOTE 1
156.25MHz f
OUT
, 25MHz crystal
Integration Range:
12kHz – 20MHz
0.233 ps
125MHz f
OUT
, 25MHz crystal
Integration Range:
12kHz – 20MHz
0.283 ps
100MHz f
OUT
, 25MHz crystal
Integration Range:
12kHz – 20MHz
0.299 ps
tsk(o) Output Skew; NOTE 2, 3 Measured on the Rising Edge 40 ps
PSNR
Power
Supply Noise
Reduction
Pin 40
(V
CC
)
From DC to 8MHz,
FORCE_LOW = HIGH
-75 dB
Pin 40
(V
CC
)
From DC to 3MHz,
FORCE_LOW = LOW
-80 dB
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 550 ps
odc Output Duty Cycle 48 52 %
