3
INDUSTRIAL TEMPERATURE RANGE
IDT5T9955
2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF
[1:0], and xDS[1:0].
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Typ. Max. Unit
C
IN Input Capacitance REF 8 10 pF
Others 5 7
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max Unit
VDDQ, VDD Supply Voltage to Ground –0.5 to +4.6 V
VI DC Input Voltage –0.5 to VDD+0.5 V
REF Input Voltage –0.5 to +4.6 V
Maximum Power T
A = 85°C 1.1 W
Dissipation TA = 55°C 1.9
T
STG Storage Temperature Range –65 to +150 °C
NOTE:
1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless xnF[1:0] = LL.
PIN DESCRIPTION
Pin Name Type Description
REF I N Reference Clock Input
xFB IN Individual Feedback Inputs for A and B banks
TEST
(1)
IN When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See
Control Summary Table) remain in effect. Set LOW for normal operation.
xsOE
(1)
IN Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q0 and x2Q1) in a LOW state
(for xPE = H) - x2Q
0 and x2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and xsOE
is HIGH, the nF[1:0] pins act as output disable controls for individual banks when xnF[1:0] = LL. Set xsOE LOW for normal operation
(has internal pull-down).
x P E I N Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/
positive edge of the reference clock (has internal pull-up).
xnF[1:0] I N 3-level inputs for selecting 1 of 9 skew taps or frequency functions
xF S I N Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A
and B banks.
xnQ[1:0] OUT Eight banks of two outputs with programmable skew
xDS[1:0] IN 3-level inputs for feedback divider selection for A and B banks
xPD IN Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).
xLOCK OUT PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
VDDQ PWR Power supply for output buffers
VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry
GND PWR Ground
