8
INDUSTRIAL TEMPERATURE RANGE
IDT5T9955
2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Min. Typ. Max. Unit
FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table
tRPWH REF Pulse Width HIGH
(1)
2——ns
tRPWL REF Pulse Width LOW
(1)
2——ns
tU Programmable Skew Time Unit See Control Summary Table
tSKEWPR Zero Output Matched-Pair Skew (xnQ0, xnQ1)
(2,3)
— 50 185 ps
tSKEW0 Zero Output Skew (All Outputs)
(4)
— 0.1 0.25 ns
tSKEWB Bank Skew
(5)
— 0.1 0.35 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
(6)
— 0.1 0.25 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
(6)
— 0.2 0.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
(6)
— 0.15 0.5 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
(2)
— 0.3 0.9 ns
tDEV Device-to-Device Skew
(2,7)
— — 0.75 ns
t(φ)1-3 Static Phase Offset (xFS = L, M, H) (FB Divide-by-n = 1, 2, 3)
(8)
−0.3 — 0.3 ns
t(φ)H Static Phase Offset (xFS = H)
(7)
−0.5 — 0.5 ns
t(φ)M Static Phase Offset (xFS = M)
(7)
−0.7 — 0.7 ns
t(φ)L1-6 Static Phase Offset (xFS = L) (xFB Divide-by-n = 1, 2, 3, 4, 5, 6)
(8)
−0.7 — 0.7 ns
t(φ)L8-12 Static Phase Offset (xFS = L) (xFB Divide-by-n = 8, 10, 12)
(8)
−1—1 ns
tODCV Output Duty Cycle Variation from 50% −1—1 ns
tPWH Output HIGH Time Deviation from 50%
(9)
— — 1.5 ns
tPWL Output LOW Time Deviation from 50%
(10)
——2 ns
tORISE Output Rise Time 0.15 0.7 1.5 ns
tOFALL Output Fall Time 0.15 0.7 1.5 ns
tLOCK PLL Lock Time
(11,12)
— — 0.5 ms
tCCJH Cycle-to-Cycle Output Jitter (peak-to-peak) — — 100
(divide by 1 output frequency, xFS = H, xFB divide-by-n=1,2)
tCCJHA Cycle-to-Cycle Output Jitter (peak-to-peak) — — 150
(divide by 1 output frequency, xFS = H, xFB divide-by-n=any)
tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak) — — 200 ps
(divide by 1 output frequency, xFS = M)
tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak) — — 200
(divide by 1 output frequency, xFS = L, FREF > 3MHz)
tCCJLA Cycle-to-Cycle Output Jitter (peak-to-peak) — — 300
(divide by 1 output frequency, xFS = L, FREF < 3MHz)
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0tU.
4. tSK(0) is the skew between outputs when they are selected for 0tU.
5. tSKEWB is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divide-
by-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs.
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
8. tφ is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on xFB.
9. Measured at 1.7V.
10. Measured at 0.7V.
11. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or xFB until tPD is within specified limits.
12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
