© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 16
1 Publication Order Number:
MC10EP445/D
MC10EP445, MC100EP445
3.3V/5V ECL 8-Bit
Serial/Parallel Converter
Description
The MC10/100EP445 is an integrated 8–bit differential serial to
parallel data converter with asynchronous data synchronization. The
device has two modes of operation. CKSEL HIGH mode is designed
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode
is designed to operate at twice the internal clock data rate of up to
5.0 Gb/s. The conversion sequence was chosen to convert the first
serial bit to Q0, the second bit to Q1, etc. Two selectable differential
serial inputs, which are selected by SINSEL, provide this device with
loop−back testing capability. The MC10/100EP445 has a SYNC pin
which, when held high for at least two consecutive clock cycles, will
swallow one bit of data shifting the start of the conversion data from
D
n
to D
n+1
. Each additional shift requires an additional pulse to be
applied to the SYNC pin.
Control pins are provided to reset and disable internal clock
circuitry. Additionally, V
BB
pin is provided for single−ended input
condition.
The 100 Series contains temperature compensation.
Features
1530 ps Propagation Delay
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
Differential Clock and Serial Inputs
V
BB
Output for Single-Ended Input Applications
Asynchronous Data Synchronization (SYNC)
Asynchronous Master Reset (RESET)
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
Open Input Default State
CLK ENABLE Immune to Runt Pulse Generation
These Devices are Pb−Free and are RoHS Compliant
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MCxxx
EP445
AWLYYWWG
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
32
1
MCxx
EP445
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
(Note: Microdot may be in either location)
MC10EP445, MC100EP445
http://onsemi.com
2
Q7
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
MC10EP445
MC100EP445
Q6 Q5 V
CC
V
CC
Q4 Q3 V
EE
V
CC
SINA SINA V
BB0
V
EE
SINB SINB SINSEL
V
CC
CKSEL
V
BB1
CLK
CLK
CKEN
RESET
V
CC
Q2
Q1
V
CC
Q0
PCLK
V
CC
PCLK
Figure 1. 32−Lead LQFP Pinout (Top View)
SYNC
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
Figure 2. 32−Lead QFN Pinout (Top View)
MC10EP445
MC100EP445
Q7 Q6 Q5 V
CC
V
CC
Q4 Q3 V
EE
V
CC
SINA SINA V
BB0
V
EE
SINB SINB SINSEL
V
CC
CKSEL
V
BB1
CLK
CLK
CKEN
RESET
V
CC
Q2
Q1
V
CC
Q0
PCLK
V
CC
PCLK
SYNC
Table 1. PIN DESCRIPTION
Pin
SINA*, SINA
*
Function
ECL Differential Serial Data Input A
SINSEL*
Q0−Q7 ECL Parallel Data Outputs
ECL Serial Input Selector Pin
CLK*, CLK* ECL Differential Clock Inputs
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC* ECL Conversion Synchronizing Input
CKSEL* ECL Clock Input Selector Pin
V
BB0
, V
BB1
Output Reference Voltage
V
CC
Positive Supply
V
EE
Negative Supply
SINB*, SINB* ECL Differential Serial Data Input B
CKEN
* ECL Clock Enable Pin
RESET* ECL Reset Pin
* Pins will default logic LOW or differential logic LOW
when left open.
EP The exposed pad (EP) on the QFN−32
package bottom is thermally connected
to the die for improved heat transfer out
of the package. THe exposed pad must
be attached to a heat−sinking conduit.
The pad is electrically connected to
V
EE
.
Exposed Pad
(EP)
MC10EP445, MC100EP445
http://onsemi.com
3
Table 2. TRUTH TABLE
PIN
FUNCTION
High Low
SINSEL Select SINB Input Select SINA Input
CKSEL
Q: PCLK = 8:1
CLK: Q = 1:1
Q
CLK
Q: PCLK = 8:1
CLK: Q = 1:2
Q
CLK
CKEN Synchronously Disable Internal Clock Circuitry Synchronously Enable Internal
Clock Circuitry
RESET Asynchronous Master Reset Synchronous Enable
SYNC Asynchronously Applied to Swallow a Data Bit Normal Conversion Process
Figure 3. Logic Diagram
Q0
1:2
DEMUX
1:2
DEMUX
1:2
DEMUX
1:2
DEMUX
Q4
Q2
Q6
Q1
Q5
Q3
Q7
1:2
DEMUX
1:2
DEMUX
1:2
DEMUX
DIV2DIV2
PCLK
PCLK
SINA
SINA
SINB
SINB
SINSEL
T
C
Q
R
CKSEL
T
C
Q
R
CKEN
CLK
CLK
RESET
SYNC
Control
Logic
V
EE

MC10EP445FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Serial to Parallel Logic Converters 3.3V/5V ECL 8-Bit Serial to Parallel
Lifecycle:
New from this manufacturer.
Delivery:
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