MC10EP445, MC100EP445
http://onsemi.com
16
0
100
200
300
400
500
600
700
800
900
1000
0 500 1000 1500 2000 2500 3000 3500
Figure 13. F
max
/Jitter
INPUT CLK FREQUENCY (MHz)
1
2
3
4
5
6
7
8
V
OUTpp
(mV)
JITTER
OUT
ps (RMS)
9
10
(JITTER)
CKSEL LOW
CKSEL HIGH
Figure 14. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50
Z
o
= 50
50 50
V
TT
V
TT
= V
CC
− 2.0 V
MC10EP445, MC100EP445
http://onsemi.com
17
ORDERING INFORMATION
Device Package Shipping
MC10EP445FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC10EP445FAR2G 2000 / Tape & Reel
MC10EP445MNG
QFN−32
(Pb−Free)
74 Units / Rail
MC10EP445MNR4G 1000 / Tape & Reel
MC100EP445FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EP445FAR2G 2000 / Tape & Reel
MC100EP445MNG
QFN−32
(Pb−Free)
74 Units / Rail
MC100EP445MNR4G 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC10EP445, MC100EP445
http://onsemi.com
18
PACKAGE DIMENSIONS
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q
_
W
K
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1
V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) Z
AC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M
_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
32 LEAD LQFP
CASE 873A−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B 7.000 BSC 0.276 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.450 0.750 0.018 0.030
M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
____
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF

MC10EP445FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Serial to Parallel Logic Converters 3.3V/5V ECL 8-Bit Serial to Parallel
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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