MC10EP445, MC100EP445
http://onsemi.com
15
The synchronous CKEN (pin 3) applied with at least one
clock cycle pulse length will disable the internal clock
signal. The synchronous CKEN
will suspend all of the
device activities and prevent runt pulses from being
generated. The rising edge of CKEN
followed by the falling
edge of CLK will suspend all activities. The first data bit will
clock on the rising edge, since the falling edge of CKEN
followed by the falling edge of the incoming clock triggers
the enabling of the internal process. (See Figure 12)
CLK
PCLK
Internal Clock
Disabled
Internal Clock
Enabled
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
CKSEL
CKEN
The differential PCLK output (pins 22 and 23) is a word
framer and can help the user to synchronize the parallel data
outputs. During CKSEL LOW operation, the PCLK will
provide a divide by 4−clock frequency, which frames the
serial data in period of PCLK output. Likewise during
CKSEL HIGH operation, the PCLK will provide a divide by
8−clock frequency.
The V
BB
pin, an internally generated voltage supply, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to V
BB
as a switching reference voltage. V
BB
may also rebias AC
coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 F capacitor, which will limit the current sourcing or
sinking to 0.5mA. When not used, V
BB
should be left open.
Also, both outputs of the differential pair must be terminated
(50 to V
TT
= V
CC
– 2 V) even if only one output is used.
