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AD600JN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
AD600/AD602
Rev. F | Page 13 of 32
The gains are offset such that the gain of A2 is increased only
after the gain of A1 has reached its maximum value (see Figure 26).
Note that, for a differential input of −700 mV or less, the gain of
a single amplifier (A1 or A2) is at its minimum value of −1.07 dB;
for a differential input of +700 mV or more, the gain is at its
maximum value of +41.07 dB. Control inputs beyond these
limits do not affect the gain and can be tolerated without damage or
foldover in the response. See the Specifications section for more
details on the allowable voltage range. The gain is now
Gain (dB) = 32 V
C
(3)
where V
C
is the applied control voltage.
+41.07dB
+20dB
+1.07dB
–0.56dB
–1.07dB
+40.56dB
+38.93dB
809.1295.0
GAIN
(dB)
*
GAIN OFFSET OF 1.07dB, OR 33.44mV
A1 A2
*
*
2.5
80
1.875
60
1.25
40
0.625
20
0
0
–2.14
V
C
(V)
82.14
00538-024
Figure 26. Explanation of Offset Calibration for Sequential Control
When V
C
is set to zero, V
G1
= −0.592 V and the gain of A1 is
1.07 dB (recall that the gain of each amplifier section is 0 dB for
V
G
= 625 mV); meanwhile, V
G2
= −1.908 V, so the gain of A2 is
−1.07 dB. The overall gain is thus 0 dB (see Figure 23). When
V
C
= 1.25 V, V
G1
= 1.25 V – 0.592 V = 0.658 V, which sets the
gain of A1 to 40.56 dB, while V
G2
= 1.25 V – 1.908 V = −0.658 V,
which sets the gain of A2 at −0.56 dB. The overall gain is now
40 dB (see Figure 24). When V
C
= 2.5 V, the gain of A1 is 41.07 dB
and the gain of A2 is 38.93 dB, resulting in an overall gain of 80
dB (see Figure 25). This mode of operation is further clarified
by Figure 27, which is a plot of the separate gains of A1 and A2
and the overall gain vs. the control voltage. Figure 28 is a plot of
the gain error of the cascaded amplifiers vs. the control voltage.
PARALLEL MODE (SIMPLEST GAIN-CONTROL
INTERFACE)
In this mode, the gain-control voltage is applied to both inputs
in parallel—C1HI and C2HI are connected to the control
voltage, and C1LO and C2LO are optionally connected to an
offset voltage of 0.625 V. The gain scaling is then doubled to
64dB/V, requiring only 1.25 V for an 80 dB change of gain. In
this case, the amplitude of the gain ripple is also doubled, as is
shown in Figure 29, and the instantaneous SNR at the output of
A2 decreases linearly as the gain is increased (see Figure 30).
LOW RIPPLE MODE (MINIMUM GAIN ERROR)
As shown in Figure 28 and Figure 29, the output ripple is
periodic. By offsetting the gains of A1 and A2 by half the
period of the ripple, or 3 dB, the residual gain errors of the two
amplifiers can be made to cancel. Figure 31 shows the much
lower gain ripple when configured in this manner. Figure 32
plots the SNR as a function of gain; it is very similar to that in
the parallel mode.
AD600/AD602
Rev. F | Page 14 of 32
0
90
20
10
50
30
40
60
70
80
OVERALL GAIN (dB)
–10
3.00–0.5 2.52.01.51.00.5
V
C
COMBINED
A1
A2
00
5
–5
–6
–2
–4
–3
–1
1
2
4
3
0
75
30
1.4
40
35
0.20
45
50
55
60
65
70
1.21.00.80.60.4
SNR (dB)
V
C
00538-028
1.2
–1.2
1.3
–0.6
–1.0
0.1
–0.8
0
0.0
–0.4
–0.2
0.2
0.4
0.6
1.0
0.8
1.21.11.00.90.70.60.50.40.3
538-025
–7
Figure 27. Plot of Separate and Overall Gains in Sequential Control
–8
3.00–0.5 1.51.00.5
V
C
Figure 30. SNR for Cascaded Stages—Parallel Control
GAIN ER
R
OR (dB)
538-026
–5
0–0.1 1.21.00.8
2.0 2.5
00
5
–3
–4
0
–2
–1
1
2
3
4
Figure 28. Gain Error for Cascaded Stages—Sequential Control
GAIN ERROR (dB)
GAIN ER
R
OR (dB)
V
C
0.2 0.8
00538-029
80
45
40
50
55
60
65
70
75
Figure 31. Gain Error for Cascaded Stages—Low Ripple Mode
35
1.40.20 1.21.00.80.60.4
V
C
0053
SNR (dB)
8-030
Figure 32. SNR vs. Control Voltage—Low Ripple Mode
V
C
–6
0.2 0.4 0.6
00538-027
Figure 29. Gain Error for Cascaded Stages—Parallel Control
AD600/AD602
Rev. F | Page 15 of 32
APPLICATIONS INFORMATION
The full potential of any high performance amplifier can be
realized only by careful attention to details in its applications.
The following pages describe fully tested circuits in which many
such details have already been considered. However, as is always
true of high accuracy, high speed analog circuits, the schematic
is only part of the story; this is no less true for the AD600/
AD602. Appropriate choices in the overall board layout and the
type and placement of power supply decoupling components
are very important. As explained previously, the input grounds
A1LO and A2LO must use the shortest possible connections.
CONT
R
OL
V
OL
T
A
GE,
+625mV
–625mV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
The following circuits show examples of time-gain control for
ultrasound and sonar, methods for increasing the output drive,
and AGC amplifiers for audio and RF/IF signal processing
using both peak and rms detectors. These circuits also illustrate
methods of cascading X-AMPs for either maintaining the
optimal SNR or maximizing the accuracy of the gain-control
voltage for use in signal measurement. These AGC circuits can
be modified for use as voltage-controlled amplifiers in sonar
and ultrasound applications by removing the detector and
substituting a DAC or other voltage source for supplying the
control voltage.
TIME-GAIN CONTROL (TGC) AND TIME-VARIABLE
GAIN (TVG)
Ultrasound and sonar systems share a similar requirement: both
need to provide an exponential increase in gain in response to a
linear control voltage, that is, a gain control that is linear in dB.
Figure 33 shows the AD600/AD602 configured for a control
voltage ramp starting at −625 mV and ending at +625 mV for a
gain-control range of 40 dB. The polarity of the gain-control
voltage can be reversed, and the control voltage inputs, C1HI
and C1LO, can be reversed to achieve the same effect. The gain-
control voltage can be supplied by a voltage output DAC, such
as the AD7244, which contains two complete DACs, operates
from ±5 V supplies, has an internal reference of +3 V, and
provides ±3 V of output swing. As such, it is well suited for use
with the AD600/AD602, needing only a few resistors to scale
the output voltage of the DACs to the levels needed by the
AD600/AD602.
REF
A1
A2
C1HI
A1CM
A1OP
VNEG
A2OP
A2CM
C2HI
C1LO
A1HI
A1LO
GAT1
A2LO
A2HI
C2LO
V
G
AD600 OR
AD602
GAT2
+5V
–5V
+
–
+
–
VPOS
VOLTAGE-OUTPUT
DAC
A1
GAIN
0dB 40dB
00538-031
V
G
VPOS
VNEG
V
IN
Figure 33. The Simplest Application of the X-AMP Is as a TGC or TVG Amplifier
in Ultrasound or Sonar (Only A1 Connections Shown for Simplicity)
INCREASING OUTPUT DRIVE
The AD600/AD602 output stage has limited capability for
negative-load driving capability. For driving loads less than
500 , the load drive can be increased by approximately 5 mA
by connecting a 1 k pull-down resistor from the output to the
negative supply (see Figure 34).
DRIVING CAPACITIVE LOADS
For driving capacitive loads of greater than 5 pF, insert a 10 
resistor between the output and the load. This lowers the
possibility of oscillation.
1kΩ
1
2
3
4
5
16
15
14
13
12
6
7
8
11
10
9
REF
A1
C1HI
A1CM
A1OP
C1LO
A1HI
A1LO
GAT1
GAIN-CONTROL
VOLTAGE
A2
A2OP
A2CM
C2HI
A2LO
A2HI
C2LO
GAT2
+5V
–5V
+
–
+
–
AD600/
AD602
PULL-DOW
RESISTOR
ADDED
N
00538-032
Figure 34. Adding a 1 kΩ Pull-Down Resistor Increases the X-AMP Output
Drive by About 5 mA (Only A1 Connections Shown for Simplicity)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

AD600JN

Mfr. #:
Buy AD600JN
Manufacturer:
Analog Devices Inc.
Description:
IC OPAMP VGA 35MHZ 16DIP
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