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ADCLK854BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADCLK854
Rev. 0 | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
V
S
= +1.8 V, T
A
= 25°C, unless otherwise noted.
CH2 100mV M 200ps 10.0GS/s CH1 –36.0mV
2
0
7218-003
CH2 100mV M 1.0ns 10.0GS/s CH1 –36.0mV
2
0
7218-006
Figure 3. LVDS Output Waveform @ 1200 MHz Figure 6. LVDS Output Waveform @ 200 MHz
2.3
2.2
2.1
2.0
1.9
1.8
1.7
0.1 1.71.51.31.10.90.70.50.3
PROPATATION DELAY (ns)
INPUT DIFFERENTIAL (V p-p)
07218-004
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
200 1600140012001000800600400
PROPAGATION DELAY (ns)
INPUT COMMON-MODE (mV)
07218-007
Figure 4. LVDS Propagation Delay vs. Input Differential Voltage (V
ID
)
Figure 7. LVDS Propagation Delay vs. V
ICM
55
45
46
47
48
49
50
51
52
53
54
0 200 400 600 800 1000 1200
DUTY CYCLE (%)
FREQUENCY (MHz)
07218-005
715
675
685
695
705
1.62 1.921.821.72
DIFFERENTIAL OUTPUT SWING (mV p-p)
POWER SUPPLY (V)
07218-008
Figure 5. LVDS Output Duty Cycle vs. Frequency Figure 8. LVDS Differential Output Swing vs. Power Supply Voltage
ADCLK854
Rev. 0 | Page 10 of 16
900
400
500
600
700
800
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
DIFFERENTIAL OUTPUT SWING (mV p-p)
INPUT FREQUENCY (MHz)
07218-009
Figure 9. LVDS Differential Output Swing vs. Input Frequency
350
325
300
275
250
225
200
175
150
125
100
75
50
25
0
0 200 400 600 800 1000 1200 1400 1600 1800
CURRENT (mA)
FREQUENCY (MHz)
07218-110
Figure 10. LVDS Current vs. Frequency; All Banks Set to LVDS
500
450
400
350
300
250
200
150
100
50
0
022.01.51.00.5
JITTER (fs rms)
INPUT SLEW RATE (V/ns)
.5
07218-011
Figure 11. Additive Broadband Jitter vs. Input Slew Rate
–
80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
10 100M10M1M100k10k1k100
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
07218-012
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT
E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A
WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),
WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A
WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).
CLOCK SOURCE
ADCLK854
Figure 12. Absolute Phase Noise LVDS @ 1000 MHz
300
0
50
100
150
200
250
25 50 75 100 125 150 175 225200 250
CURRENT (mA)
FREQUENCY (MHz)
07218-113
ALL BANKS CMOS
2 BANKS CMOS
1 BANK LVDS
1 BANK CMOS
2 BANKS LVDS
ALL BANKS LVDS
Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic
Combinations
55
45
46
47
48
49
50
51
52
53
54
0 50 100 150 200 250
DUTY CYCLE (%)
FREQUENCY (MHz)
07218-014
Figure 14. CMOS Output Duty Cycle vs. Frequency (10 pF Load)
ADCLK854
Rev. 0 | Page 11 of 16
CH1 300mV 1.25ns/DIV CH1 954mV
1
0
7218-015
CH1 300mV 5.0ns/DIV CH1 954mV
1
0
7218-018
Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load) Figure 18. CMOS Output Waveform @ 50 MHz (10 pF Load)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
50 100 150 200 250
OUTPUT SWING (V)
FREQUENCY (MHz)
25°C
85°C
07218-016
1.8
1.4
1.5
1.6
1.7
0220015010050
OUTPUT SWING (V)
FREQUENCY (MHz)
50
R
LOAD
= 1kΩ
R
LOAD
= 750Ω
R
LOAD
= 500Ω
R
LOAD
= 300Ω
07218-019
Figure 16. CMOS Output Swing vs. Frequency by Temperature (10 pF Load) Figure 19. CMOS Output Swing vs. Frequency by Resistive Load
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0 50 100 150 200 250
C
L
= 5pF
C
L
= 10pF
C
L
= 20pF
OUTPUT SWING (V)
FREQUENCY (MHz)
07218-017
Figure 17. CMOS Output Swing vs. Frequency by Capacitive Load
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADCLK854BCPZ

Mfr. #:
Buy ADCLK854BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 1.8V 12-LVDS/24-CMOS Output Lw Pwr
Lifecycle:
New from this manufacturer.
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