ADCLK854
Rev. 0 | Page 15 of 16
still meet receiver input requirements in some applications. This
can be useful when driving long trace lengths on less critical
networks.
CMOS CMOS
10Ω
50Ω
100Ω
100Ω
S
07218-027
Figure 27. CMOS Output with Far End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The ADCLK854 offers LVDS outputs
that are better suited for driving long traces wherein the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
INPUT TERMINATION OPTIONS
For single-ended operation always bypass unused input to
GND, as shown in Figure 31.
Figure 32 illustrates the use of V
REF
to provide low impedance
termination into V
S
/2. In addition, a way to negate the 30 mV
input offset is with external resistor values; for example, using a
1.8 V CMOS with long traces to provide far end termination.
100Ω
CLK
CLK
100Ω
CLK
CLK
7218-028
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration
(See Table 8 for More Information)
CLK
CLK
CLK
CLK
CC
V
CC
7218-029
Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration
(See Table 8 for CML Coupling Limitations)
CLK
CLK
50Ω 50Ω
V
CC
– 2V
CLK
CLK
50Ω 50Ω
V
CC
– 2V
07218-030
Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration
(See Table 8 for LVPECL DC-Coupling Limitations)
CLK
CLK
CLK
CLK
CLK
CLK
07218-031
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths
(See Table 8 for CMOS Compatibility)
CLK
CLK
V
REF
07218-032
Figure 32. Use of V
REF
to Provide Low Impedance Termination into V
S
/2
