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ADCLK854BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADCLK854
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for V
S
= 1.8 V and T
A
= 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over
the full V
S
= 1.8 V ± 5% and T
A
= −40°C to +85°C variation, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter Symbol Min Typ Max Unit Conditions
CLOCK INPUTS Differential input
Input Frequency 0 1200 MHz
Input Sensitivity, Differential 150 mV p-p Jitter performance improves with higher slew
rates (greater voltage swing)
Input Level 1.8 V p-p Larger voltage swings can turn on the protection
diodes and degrade jitter performance
Input Common-Mode Voltage V
CM
V
S
/2 − 0.1 V
S
/2 + 0.5 V Inputs are self-biased; enables ac coupling
Input Common-Mode Range V
CMR
0.4 V
S
− 0.4 V Inputs dc-coupled with 200 mV p-p signal applied
Input Voltage Offset 30 mV
Input Sensitivity, Single-Ended 150 mV p-p
CLKx ac-coupled;
CLKx
ac bypassed to ground
Input Resistance (Differential) 7 kΩ
Input Capacitance C
IN
2 pF
Input Bias Current (Each Pin) −350 +350 µA Full input swing
LVDS CLOCK OUTPUTS
Termination = 100 Ω; differential (OUTx,
OUTx
)
Output Frequency 1200 MHz See Figure 9 for swing vs. frequency
Output Voltage Differential V
OD
247 344 454 mV
Delta V
OD
V
OD
50 mV
Offset Voltage V
OS
1.125 1.25 1.375 V
Delta V
OS
V
OS
50 mV
Short-Circuit Current I
S
A, I
S
B 3 6 mA Each pin (output shorted to GND)
CMOS CLOCK OUTPUTS Single-ended; termination = open; OUTx and
OUTx
in phase
Output Frequency 250 MHz With 10 pF load per output; see Figure 16 for
swing vs. frequency
Output Voltage High V
OH
V
S
− 0.1 V @ 1 mA load
Output Voltage Low V
OL
0.1 V @ 1 mA load
Output Voltage High V
OH
V
S
− 0.35 V @ 10 mA load
Output Voltage Low V
OL
0.35 V @ 10 mA load
Reference Voltage V
REF
Output Voltage V
S
/2 − 0.1 V
S
/2 V
S
/2 + 0.1 V ±500 µA
Output Resistance 60 Ω
Output Current 500 µA
ADCLK854
Rev. 0 | Page 4 of 16
TIMING CHARACTERISTICS
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit Conditions
LVDS OUTPUTS Termination = 100  differential; 3.5 mA
Output Rise/Fall Time t
R
, t
F
135 235 ps 20% to 80% measured differentially
Propagation Delay, Clock-to-LVDS Output t
PD
1.5 2.0 2.7 ns V
ICM
= V
REF
, V
ID
= 0.5 V
Temperature Coefficient 2.0 ps/°C
Output Skew
1
LVDS Outputs in the Same Bank 50 ps
All LVDS Outputs
On the Same Part 65 ps
Across Multiple Parts 390 ps
Additive Time Jitter
Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz
74 fs rms BW = 50 kHz to 80 MHz; clock = 1000 MHz
86 fs rms BW = 10Hz to 100 MHz; clock = 1000 MHz
Broadband Random Jitter
2
150 fs rms Input slew = 1 V/ns, see Figure 11
Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an
interferer 10 MHz offset from the carrier
CMOS OUTPUTS
Output Rise/Fall Time t
R,
t
F
525 950 ps 20% to 80%; C
LOA D
= 10 pF
Propagation Delay, Clock-to-CMOS Output t
PD
2.5 3.2 4.2 ns 10 pF load
Temperature Coefficient 2.2 ps/°C
Output Skew
1
CMOS Outputs in the Same Bank 155 ps
All CMOS Outputs
On the Same Part 175 ps
Across Multiple Parts 640 ps
Additive Time Jitter
Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz; clock = 200 MHz
Broadband Random Jitter
2
100 fs rms Input slew = 2 V/ns, see Figure 11
Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an
interferer 10 MHz offset from the carrier
LVDS-TO-CMOS OUTPUT SKEW
3
LVDS Output(s) and CMOS Output(s) on the
Same Part
0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω
1
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Calculated from the SNR of the ADC method.
3
Measured at the rising edge of the clock signal.
ADCLK854
Rev. 0 | Page 5 of 16
CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter Min Typ Max Unit Conditions
CLOCK-TO-LVDS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
1000 MHz −90 dBc/Hz @ 10 Hz offset
−108 dBc/Hz @ 100 Hz offset
−117 dBc/Hz @ 1 kHz offset
−126 dBc/Hz @ 10 kHz offset
−135 dBc/Hz @ 100 kHz offset
−141 dBc/Hz @ 1 MHz offset
−146 dBc/Hz @ 10 MHz offset
CLOCK-TO-CMOS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
200 MHz −101 dBc/Hz @ 10 Hz offset
−119 dBc/Hz @ 100 Hz offset
−127 dBc/Hz @ 1 kHz offset
−138 dBc/Hz @ 10 kHz offset
−147 dBc/Hz @ 100 kHz offset
−153 dBc/Hz @ 1 MHz offset
−156 dBc/Hz @ 10 MHz offset
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter Symbol Min Typ Max Unit Conditions
CONTROL PINS (IN_SEL, CTRL_x, SLEEP)
1
Logic 1 Voltage V
IH
V
S
− 0.4 V
Logic 0 Voltage V
IL
0.4 V
Logic 1 Current I
IH
5 8 20 A
Logic 0 Current I
IL
−5 +5 A
Capacitance 2 pF
POWER
Supply Voltage Requirement V
S
1.71 1.8 1.89 V V
S
= 1.8 V ± 5%
LVDS Outputs Full operation
LVDS @ 100 MHz 84 100 mA All outputs enabled as LVDS and loaded, R
L
= 100 
LVDS @ 1200 MHz 175 215 mA All outputs enabled as LVDS and loaded, R
L
= 100 
CMOS Outputs
Full operation
CMOS @ 100 MHz 115 140 mA All outputs enabled as CMOS and loaded, C
L
= 10 pF
CMOS @ 250 MHz 265 325 mA All outputs enabled as CMOS and loaded, C
L
= 10 pF
SLEEP
3 mA SLEEP pin pulled high; does not include power dissipated
in the external resistors
Power Supply Rejection
2
LVDS
PD
t
PSR
0.9 ps/mV
CMOS
PD
t
PSR
1.2 ps/mV
1
These pins each have a 200 kΩ internal pull-down resistor.
2
Change in t
PD
per change in V
S
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADCLK854BCPZ

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Buy ADCLK854BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 1.8V 12-LVDS/24-CMOS Output Lw Pwr
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