ISL6535
10
FN9255.3
March 3, 2016
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Compensating the Converter
The ISL6535 Single-phase converter is a voltage-mode controller.
This section highlights the design consideration for a voltage-mode
controller requiring external compensation. To address a broad
range of applications, a type-3 feedback network is
recommended (see Figure 9
).
Figure 10
highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to provide a
pulse-width modulated wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output filter. The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a DC gain
and shaped by the output filter, with a double pole break
frequency at F
LC
and a zero at F
CE
. For the purpose of this
analysis, L and DCR represent the output inductance and its
DCR, while C and ESR represents the total output capacitance
and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R
1
to R
3
, C
1
to C
3
components. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing frequency
(F
0
; typically 0.1 to 0.3 of f
SW
) and adequate phase margin
(better than 45°). Phase margin is the difference between the
closed loop phase at F
0dB
and 180°. The equations that follow
relate the compensation network’s poles, zeros and gain to the
components (R
1
, R
2
, R
3
, C
1
, C
2
and C
3
) in Figures 9 and 10.
Use the following guidelines for locating the poles and zeros of
the compensation network:
1. Select a value for R
1
(1kΩ to 10kΩ, typically). Calculate value
for R
2
for desired converter bandwidth (F
0
). If setting the
output voltage to be equal to the reference set voltage, as
shown in Figure 10
, the design procedure can be followed as
presented.
As the ISL6535 supports 100% duty cycle, DMAX equals 1.
The ISL6535 uses a fixed ramp amplitude (V
OSC
) of 1.9V,
Equation 8 simplifies to Equation 9:
2. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor in
Equation 10
to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio F
CE
/F
LC
,
the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
3. Calculate C
2
such that F
P1
is placed at F
CE
.
4. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such
that F
P2
is placed below f
SW
(typically, 0.3 to 1.0 times f
SW
).
f
SW
represents the switching frequency of the regulator.
Change the numerical factor (0.7) below to reflect desired
placement of this pole. Placement of F
P2
lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
It is recommended that a mathematical model be used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 11 on page 11 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain has a
high gain peak dependent on the quality factor (Q) of the output
filter, which is not shown. Using the previously mentioned
guidelines should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
against
the capabilities of the error amplifier. The closed loop gain, G
CL
,
is constructed on the log-log graph of Figure 11
by adding the
modulator gain, G
MOD
(in dB), to the feedback compensation
gain, G
FB
(in dB). This is equivalent to multiplying the modulator
transfer function and the compensation transfer function and
then plotting the resulting gain.
F
LC
1
2 LC
---------------------------
=
F
CE
1
2 C ESR
---------------------------------
= (EQ. 7)
R
2
V
OSC
R
1
F
0

D
MAX
V
IN
F
LC

----------------------------------------------
=
(EQ. 8)
R
2
1.9 R
1
F
0

V
IN
F
LC
-------------------------------
= (EQ. 9)
C
1
1
2 R
2
0.5 F
LC

-----------------------------------------------
=
(EQ. 10)
R
3
R
1
f
SW
F
LC
-----------
1
--------------------
=
C
3
1
2 R
3
0.7 f
SW

-----------------------------------------------
=
(EQ. 12)
G
MOD
f
D
MAX
V
IN
V
OSC
-------------------------------
1sf ESR C+
1sf ESR DCR+Cs
2
f LC++
-----------------------------------------------------------------------------------------------------------
=
G
FB
f
1sf R
2
C
1
+
sf R
1
C
1
C
2
+
----------------------------------------------------
=
1sf R
1
R
3
+C
3
+
1sf R
3
C
3
+1sf R
2
C
1
C
2
C
1
C
2
+
---------------------



+



-------------------------------------------------------------------------------------------------------------------------
G
CL
f G
MOD
f G
FB
f=
where s f 2 fj=
(EQ. 13)
F
Z1
1
2 R
2
C
1

-------------------------------
=
F
Z2
1
2 R
1
R
3
+C
3

-------------------------------------------------
=
F
P1
1
2 R
2
C
1
C
2
C
1
C
2
+
---------------------

---------------------------------------------
=
F
P2
1
2 R
3
C
3

-------------------------------
=
(EQ. 14)
ISL6535
11
FN9255.3
March 3, 2016
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A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of the
switching frequency, f
SW
.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the
load transient current. The filtering requirements are a function
of the switching frequency and the ripple current. The load
transient requirements are a function of the slew rate (di/dt) and
the magnitude of the transient load current. These requirements
are generally met with a mix of capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating requirements
rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as close
to the power pins of the load as physically possible. Be careful
not to add inductance in the circuit board wiring that could
cancel the usefulness of these low inductance components.
Consult with the manufacturer of the load on specific decoupling
requirements.
Use only specialized low-ESR capacitors intended for switching
regulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor's ESR value is related to the case size with
lower ESR available in larger case sizes. However, the equivalent
series inductance (ESL) of these capacitors increases with case
size and can reduce the usefulness of the capacitor to high
slew-rate transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
Equation 15
:
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a load
transient is the time required to change the inductor current. Given
a sufficiently fast control loop design, the ISL6535 will provide
either 0% or 100% duty cycle in response to a load transient. The
response time is the time required to slew the inductor current
from an initial current value to the transient current level. During
this interval the difference between the inductor current and the
transient current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient load is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
Where I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high frequency decoupling and bulk capacitors to supply the
current needed each time Q
1
turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
drain of Q
1
and the source of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable operation,
select a bulk capacitor with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. The capacitor voltage rating should be at least 1.25x
greater than the maximum input voltage, a voltage rating of 1.5x
greater is a conservative guideline. The RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
GAIN
FREQUENCY
MODULATOR GAIN
CLOSED LOOP GAIN
20
D
MAX
V
IN
V
OSC
----------------------------------log
20
R
2
R
1
--------



log
LOG
LOG
F
0
G
MOD
G
FB
G
CL
V
OUT
= I x ESR
I =
V
IN
- V
OUT
Fs x L
--------------------------------
V
OUT
V
IN
----------------
(EQ. 15)
t
FALL
L
O
I
TRAN
V
OUT
-------------------------------
=t
RISE
L
O
I
TRAN
V
IN
V
OUT
--------------------------------
=
(EQ. 16)
ISL6535
12
FN9255.3
March 3, 2016
Submit Document Feedback
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or
equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. The TPS series available from AVX, and the 593D
series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6535 requires at least two N-channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate supply
requirements and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. At a 300kHz switching frequency, the
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs. These
losses are distributed between the two MOSFETs according to
duty factor (see Equation 17
). Only the upper MOSFET exhibits
switching losses, since the schottky rectifier clamps the
switching node before the synchronous rectifier turns on.
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse recovery of
the lower MOSFETs body diode. The gate-charge losses are
dissipated by the ISL6535 and don't heat the MOSFETs. However,
large gate-charge increases the switching interval, t
SW
which
increases the upper MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for use with
the ISL6535. However, logic-level gate MOSFETs can be used
under special circumstances. The input voltage, upper gate drive
level, and the MOSFETs absolute gate-to-source voltage rating
determine whether logic-level MOSFETs are appropriate.
Figure 12
shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from +12V. The boot capacitor, C
BOOT
develops
a floating supply voltage referenced to the PHASE pin. This
supply is refreshed each cycle to a voltage of +12V less the boot
diode drop (V
D
) when the lower MOSFET, Q
2
turns on. A MOSFET
can only be used for Q
1
if the MOSFETs absolute gate-to-source
voltage rating exceeds the maximum voltage applied to +12V.
For Q
2
, a logic-level MOSFET can be used if its absolute
gate-to-source voltage rating also exceeds the maximum voltage
applied to +12V.
Figure 13
shows the upper gate drive supplied by a direct
connection to +12V. This option should only be used in converter
systems where the main input voltage is +5 V DC or less. The peak
upper gate-to-source voltage is approximately +12V less the input
supply. For +5V main power and +12V DC for the bias, the
gate-to-source voltage of Q
1
is 7V. A logic-level MOSFET is a good
choice for Q
1
and a logic-level MOSFET can be used for Q
2
if its
absolute gate-to-source voltage rating exceeds the maximum
voltage applied to PVCC. This method reduces the number of
required external components, but does not provide for immunity to
phase node ringing during turn on and may result in lower system
efficiency.
Schottky Selection
Rectifier D
2
is a clamp that catches the negative inductor swing
during the dead time between turning off the lower MOSFET and
turning on the upper MOSFET. The diode must be a Schottky type
to prevent the lossy parasitic MOSFET body diode from conducting.
It is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but efficiency
could slightly decrease as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.
P
UPPER
= I
O
2
x r
DS(ON)
x D +
1
2
Io x V
IN
x t
SW
x f
SW
P
LOWER
= I
O
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
O
/ V
IN
,
t
SW
is the switching interval, and
f
SW
is the switching frequency.
(EQ. 17)
FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION
FIGURE 13. UPPER GATE DRIVE - DIRECT V
CC
DRIVE OPTION
+12V
PGND
ISL6535
GND
LGATE
UGATE
BOOT
+1.2V TO +12V
NOTE:
V
G-S
V
CC
- V
D
NOTE:
V
G-S
PVCC
C
BOOT
D
BOOT
Q1
Q2
PVCC
+12V
D2
+
-
V
D
+
-
PHASE
+12V
PGND
LGATE
UGATE
BOOT
+5V OR LESS
NOTE:
V
G-S
V
CC
- 5V
NOTE:
V
G-S
PVCC
Q1
Q2
PV
CC
+12V
D2
ISL6535
GND
+
-

ISL6535CBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers PWM CNTRLR DDRG 14LD N
Lifecycle:
New from this manufacturer.
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