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NCV8851DBR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
NCV8851
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This sequence begins once V
IN_IC
surpasses its UVLO
threshold when the part is enabled and the LDO output has
risen. After an initial delay to assure a clean start−up,
switching begins, the output initially rises quickly and then
rises monotonically. The duty cycle is gradually increased
until V
OUT
has reached its set point or until maximum duty
cycle is reached.
Normal Shutdown Behavior and Sleep Mode
Normal shutdown occurs when the IC stops switching
because the input supply drops below the UVLO threshold,
the part enters TSD or the part is disabled. When disabled,
the part enters sleep mode.
In sleep mode, the LDO turns off and its output capacitor
discharges, causing switching to stop, the internal soft−start
capacitor to discharge and GH and GL to go low. The switch
node enters a high impedance state and the output inductor
and capacitors discharge through the load. The supply
current reduces to the sleep mode quiescent current.
Internal Linear Regulator (LDO)
The NCV8851 has an onboard low−dropout linear
regulator (LDO) internally connected to drive the low−side
gate. The 6V
OUT
pin should be externally connected to the
V
IN_IC
pin to power the internal rails. Typically, a RC filter
is used from 6V
OUT
to V
IN_IC
to further decrease noise on
the internal rails.
The 6V
OUT
pin should be externally connected through a
diode to the BST pin, charging the BST capacitor during
off−time to generate a voltage for the high−side driver.
When the part is enabled and V
IN
is below the LDO
regulated value, the LDO is in dropout and it tracks V
IN
. The
LDO regulates its output once V
IN
is above the output set
point plus the dropout voltage.
An external bypass capacitor must be connected from
6V
OUT
to ground. A short to ground or overcurrent
condition on the 6V
OUT
pin will be mitigated by the LDO
current limit and internal thermal shutdown (TSD) circuitry
which disables all outputs. A normal soft−start will occur
when the die temperature falls below the TSD threshold.
Drivers
The NCV8851 includes 1.5 A gate drivers to switch
external N−Channel MOSFETs. This allows the NCV8851
to address high−power, as well as low−power conversion
requirements. The gate drivers also include adaptive
non−overlap circuitry. The non−overlap circuitry increases
efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time, while
protecting against cross−conduction (shoot−through) of the
MOSFETs. A detailed block diagram of the non−overlap
and gate drive circuitry used in the chip and related external
components is shown in Figure 23.
PGND
GH
GL
BST
Main
PWM
Output
MainFault
GL
Threshold
Threshold
GL to GH
Delay
GH to GL
Delay
Figure 23. Gate Driver Block Diagram
Fault
V
SW
V
SW
V
SW
6V
OUT
A capacitor is placed from V
SW
to BST and a diode is
placed from 6V
OUT
to BST to create a bootstrap supply on
the BST pin for the high−side floating gate driver. This
ensures that the voltage on BST is about 6V
OUT
higher than
V
SW
, less a diode drop, yielding a gate drive voltage high
enough to enhance the high−side MOSFET. The BST
capacitor supplies the charge used by the gate driver to
charge up the input capacitance of the high−side MOSFET,
and is typically chosen to be at least a decade larger than this
capacitance. A 0.1 mF BST capacitor is recommended.
Since the BST capacitor only recharges when the
low−side MOSFET is on, pulling V
SW
down to ground, the
NCV8851 has a minimum off−time. This also means that the
BST capacitor cannot be arbitrarily large, since 6V
OUT
needs to be able to charge it up during this minimum
off−time so the high−side gate driver doesn’t run out of
headroom. 6V
OUT
needs to supply charge both to the BST
capacitor and also the low−side driver, so the LDO capacitor
must be sufficiently larger than the BST capacitor. A 1 mF
LDO capacitor is recommended.
NCV8851
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Careful selection and layout of external components is
required to realize the full benefit of the onboard drivers.
The capacitors between V
IN
and GND and between BST
and V
SW
must be placed as close as possible to the IC. The
current paths for the GH and GL connections must be
optimized, minimizing parasitic resistance and inductance.
Current Limiting and Overcurrent Protection
The NCV8851 contains average current limiting (ACL)
and cycle−by−cycle overcurrent protection (OCP) to protect
the power switches, inductor, current sense resistor and
other external components. The current through the inductor
is continuously sensed using the CSP and CSN pins. A sense
resistor is placed between these pins to translate the output
current to a proportional voltage. This voltage is compared
to a fixed internal voltage threshold.
When the differential voltage exceeds the ACL threshold,
the PWM pulse is terminated for this cycle, limiting the
current through the inductor. In steady−state operation,
decreasing the load resistance while in ACL will cause the
duty cycle and V
OUT
to decrease proportionally without
skipping pulses or jitter.
There is also a fast OCP path which is tripped when the
differential voltage exceeds the OCP threshold, which is
above the ACL threshold. This causes the PWM pulse to be
terminated very quickly and disables the part from switching
back on until the current through the inductor has dropped
below the OCP threshold. Once the inductor current is below
the OCP threshold, the part will begin switching again and
the current will be limited by ACL, until the inductor current
drops below the ACL threshold.
An advantage of this current limiting scheme is that the
NCV8851 will limit large transient currents yet resume
normal operation on the following cycle. Additionally, the
current will not run away, nor will the part latch off in case
of a short, which is typical of other current limiting schemes
employing high−side current sensing.
SYNC Feature
An external clock signal can synchronize the NCV8851 to
a higher frequency. The rising edge of the SYNC pulse turns
on the power switch to start a new switching cycle, as shown
in Figure 24. There is a 0.5 ms delay between the rising edge
of the SYNC pulse and rising edge of the V
SW
pin voltage.
The SYNC threshold is TTL logic compatible, and duty
cycle of the SYNC pulses can vary from 10% to 90%. The
SYNC frequency must be higher than the internal oscillator
frequency set by R
OSC
.
Figure 24. Synchronization from 170 kHz to an external 600 kHz signal
Snubber
A snubber consisting of a 4300 pF ceramic capacitor and
a 1 W reistor from switch node to ground is required to
decrease noise susceptibility. The resistor should be rated for
0.5 W of power dissipation for switching frequencies below
280 kHz and 1 W of power dissipation for switching
frequencies above 280 kHz. The snubber should be placed
close to the switch node pin.
NCV8851
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APPLICATIONS INFORMATION
Design Methodology
Choosing external components for the NCV8851
encompasses the following design process:
1. Define operational parameters
2. Select switching frequency
3. Select current sensor
4. Select output inductor
5. Select output capacitors
6. Select input capacitors
7. Select compensator components
(1) Operational Parameter Definition
Before proceeding with the rest of the design, certain
operational parameters must be defined. These are
application−dependent and include the following:
V
IN
: input voltage, range from minimum to
maximum with a typical value [V]
V
OUT
: output voltage [V]
I
OUT
: output current, range from minimum to
maximum with initial start−up value [A]
I
CL
: desired typical current−limit [A]
A number of basic calculations must be performed
up−front to use in the design process, as follows:
D
MIN
+
V
OUT
V
IN(max)
D +
V
OUT
V
IN(typ)
D
MAX
+
V
OUT
V
IN(min)
Where: D
MIN
: minimum duty cycle (ideal) [%]
V
IN(max)
: maximum input voltage [V]
D: typical duty cycle (ideal) [%]
V
IN(typ)
: typical input voltage [V]
D
MAX
: maximum duty cycle (ideal) [%]
V
IN(min)
: minimum input voltage [V]
It should be noted that these are the ideal duty cycles; the
actual duty cycles will be marginally higher than these
calculated values. The actual duty cycles are dependent on
load due to voltage drops in the MOSFETs, inductor and
current sensor.
(2) Switching Frequency Selection
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values to achieve the same inductor current ripple
and output voltage ripple. However, increasing the
frequency increases the switching losses of the MOSFETs,
leading to decreased efficiency, especially noticeable at light
loads.
Typically, the switching frequency is selected to avoid
interfering with signals of known frequencies. Often, in this
case, the frequency can be programmed to a lower value
with R
OSC
and then a higher−frequency signal can be
applied to the SYNC pin to increase the frequency
dynamically to avoid given frequencies. A spread spectrum
signal could also be used for the SYNC input, as long as the
lowest frequency in the range is above the programmed
frequency set by R
OSC
. Additionally, the highest SYNC
frequency must not exceed maximum switching frequency
limits.
There are two limits on the maximum allowable switching
frequency: minimum off−time and minimum on−time.
These set two different maximum switching frequencies, as
follows:
F
SW(max)1
+
1 * D
MAX
T
MinOff
F
SW(max)2
+
D
MIN
T
MinOn
Where: F
SW(max)1
: maximum switching frequency due to
minimum off−time [Hz]
T
MinOff
: minimum off−time [s]
F
SW(max)2
: maximum switching frequency due to
minimum on−time [Hz]
T
MinOn
: minimum on−time [s]
Alternatively, the minimum and maximum operational
input voltage can be calculated as follows:
V
IN(min)
+
V
OUT
1 * T
MinOff
@ F
SW
V
IN(max)
+
V
OUT
T
MinOn
@ F
SW
Where: F
SW
: switching frequency [Hz]
The switching frequency is programmed by selecting the
resistor connected between the R
OSC
pin and ground. The
grounded side of this resistor should be directly connected
to the AGND pin. Avoid running any noisy signals under the
resistor, since injected noise could cause frequency jitter.
The graph in Figure 25 shows the required resistance to
program the frequency. From 150 to 450 kHz, the following
formula is accurate to within 3%:
R
OSC
+
8687000
F
SW
Where: R
OSC
: frequency program resistor [W]
Some specific values for switching frequency with
standard 1% resistors can be seen in Table 1.
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NCV8851DBR2G

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Manufacturer:
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LDO Voltage Controllers AUTOMTVE GRD SYNCHRN
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