OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCV8851DBR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
NCV8851
http://onsemi.com
7
TYPICAL CHARACTERISTICS
(T
A
= +25°C, V
IN
= 13.2 V, R
OSC
= 51.1 kW, unless otherwise noted)
96%
97%
98%
99%
100%
101%
102%
−50 0 50 100 150
Ambient Temperature (°C)
Switching Frequency (%)
170 kHz 360 kHz 500 kHz
20
25
30
35
40
45
50
55
60
65
70
−50 0 50 100 150
Ambient Temperature (°C)
Delay (ns)
GH to GL GL to GH
98%
100%
102%
104%
106%
108%
−50 0 50 100 150
Ambient Temperature (°C)
Minimum Pulse Width (%)
99.50%
99.75%
100.00%
100.25%
100.50%
0.00 5.00 10.00 15.00 20.00
LDO Load Current (mA)
6V
OUT
(V)
0.1
1
10
100
1000
0 5 10 15 20
LDO Load Current (mA)
Output Capacitor ESR (Ω)
UNSTABLE
UNSTABLE
(0.1uF only)
STABLE
50
60
70
80
90
100
110
120
130
−50 0 50 100 150
Ambient Temperature (°C)
Dropout Voltage (mV)
93%
0
20
40
60
80
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Load Current (A)
Efficiency (%)
Figure 12. Oscillator Frequency
vs. Temperature
Figure 13. Non−Overlap Delay vs.
Temperature
Figure 14. GH Minimum Pulse
Width vs. Temperature
Figure 15. LDO Load Regulation Figure 16. LDO Stability Region Figure 17. LDO Dropout Voltage vs.
Temperature
Figure 18. Efficiency vs. Load
Current 5 V, 170 kHz Demo Board
NCV8851
http://onsemi.com
8
DETAILED OPERATING DESCRIPTION
General
The NCV8851 is a synchronous buck controller with
internal 1.5 A gate drivers designed to drive NMOS FETs.
The internal gate drivers simplify design, improve
performance and efficiency and minimize board area. The
controller uses an 800 mV, 2.0% reference, allowing for a
wide range of precise output voltage programmability.
The NCV8851 also provides a programmable fixed
frequency range of 170 kHz to 500 kHz, allowing more
design flexibility in compromising efficiency versus
components’ size and cost. This frequency is conveniently
set with an external resistor to ground. An external clock
signal can also be used to synchronize the NCV8851 to a
higher operating frequency during operation.
To protect against possible damage of external
power−stage components, excessive inrush of current
during start−up is prevented by an internal soft−start, and
inductor current is limited via average current limiting
(ACL) and cycle−by−cycle overcurrent protection (OCP).
Thermal shutdown (TSD) is also implemented to protect the
device from overheating.
Average Current Mode Control
The NCV8851 employs an average current mode control
(ACMC) architecture to regulate the output voltage. ACMC
uses two loops, as seen in Figure 19. Through the current
error amplifier (CEA), the inner current loop monitors the
inductor current with the unity gain current sense amplifier
(CSA). The current loop responds to input voltage changes,
affecting the line transient response. Using the voltage error
amplifier (VEA), the outer voltage loop monitors the output
voltage, responding to output load changes, affecting the
load transient response. Feedback resistors in the voltage
loop select the output voltage.
L
−
+
CSA
−
+
VEA
−
+
CEA
C
PWM
and
Gate Drivers
Inner
Current
Loop
Outer Voltage Loop
Gain=1
Figure 19. ACMC Loops
V
SW
R
S
R
L
V
OUT
V
REF
Unlike voltage mode control (VMC) of buck regulators,
which almost always require the extra components of a
Type−III compensation network for adequate transient
response, ACMC buck regulators use Type−II
compensation. This greatly simplifies the compensator
design and optimization process, while offering much faster
transient response than a Type−I compensation network.
Additionally, the two−loop system separates the effects of
output components between the two loops, further
simplifying the compensation process.
Type−II compensation places a zero and two poles in each
of the error loops to offset the effects of the inherent
open−loop response. This compensation requires a resistor
and two capacitors in the feedback loop for each of the error
amplifiers, shown as complex impedances in Figure 19. An
input resistor from the CSA to the CEA sets the gain of the
CEA. The voltage loop also has a pair of feedback resistors
from V
OUT
to set the output voltage and gain of the VEA.
Enable
The enable input (EN) is a TTL−compatible input used to
activate the internal LDO. The NCV8851 is disabled when
the EN pin is pulled below the enable input logic low
threshold voltage, causing a normal shutdown to occur,
putting the part into a low quiescent current sleep mode.
When the EN pin is pulled above the enable input logic high
threshold voltage, the part is enabled, the LDO output is
brought up and then the internal soft−start begins.
NCV8851
http://onsemi.com
9
EN
125 kΩ
22 V 5.4 V
Internal
Enable
Figure 20. Enable Pin Equivalent Structure
R
EN
V
IN
D
ZEN2
D
ZEN1
The EN pin can be tied to V
IN
in order to enable the part.
If EN is above 22 V, D
ZEN2
will be conducting, as well as
D
ZEN1
. The current to D
ZEN1
is limited by an internal
125 kW resistor. If D
ZEN2
is conducting, it is recommended
at least 250 mA is pulled through this diode. The resistor R
EN
must be used if V
IN
can go above 20 V as follows.
R
EN(max)
+
V
Z
250 mA
Where V
Z
is the amount of volts where D
ZEN2
is conducting,
but not yet supplied with 250 mA. For example, setting V
Z
to 1 V means R
EN
must be less than 4 kW for D
ZEN2
to have
at least 250 mA when V
IN
is at least 23 V; for the range of V
IN
between 22 V and 23 V, D
ZEN2
will be conducting, but not
with the recommended 250 mA current.
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V
IN_IC
is too low
to support the internal rails and power the controller. The IC
will start up when enabled and V
IN_IC
surpasses the UVLO
threshold and will shutdown when V
IN_IC
drops below the
UVLO threshold minus the UVLO hysteresis. While V
IN
is
less than the set point for V
OUT
, the output will run at max
duty cycle, after soft−start, once V
IN_IC
surpasses the
UVLO threshold. If EN is high and not tied to V
IN
, the
output will begin to rise up while in UVLO, if a minimum
output load of 1 kW is not met.
Thermal Shutdown
The NCV8851 provides Thermal Shutdown (TSD),
which monitors the die temperature and turns off the top and
bottom gate drivers if an over temperature condition is
detected, for added protection. The internal soft−start
capacitor is also discharged. A normal soft−start will occur
when the die temperature falls below the TSD threshold
minus the TSD hysteresis.
Duty Cycle and Maximum Pulse Width Limits
In steady state dc operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. There is a built in minimum off−time which
ensures that the bootstrap supply is charged every cycle,
determining the maximum duty cycle at a given frequency.
The NCV8851 can achieve at least a 95% duty cycle while
operating at frequencies up to 200 kHz (89% at up to
500 kHz).
Internal Soft−Start
The NCV8851 features an internal soft−start function,
which reduces inrush current and overshoot of the output
voltage. Figures 21 and 22 show a typical soft−start
sequence.
UVLO
Threshold
Figure 21. Normal Start−up
Figure 22. Switch−node in Soft−Start
V
SW
t
Soft−start Time
90%*V
OUT
10%*V
OUT
Soft−start Delay
V
IN
V
OUT
t
6V
OUT
and
V
IN_IC
Soft−start is achieved by ramping up the internal soft−start
voltage (V
SS
), which is applied to the non−inverting input of
the voltage error amplifier, effectively limiting the slew rate
of V
OUT
rising. This ramp is generated by charging an
internal soft−start capacitor based on the internal oscillator,
causing the soft−start time to be inversely related to the
frequency set by R
OSC
. The internal soft−start capacitor is
discharged when the part is disabled, enters TSD or enters
UVLO, ensuring a proper start−up when the part is
re−enabled, leaves TSD or leaves UVLO.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

NCV8851DBR2G

Mfr. #:
Buy NCV8851DBR2G
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Controllers AUTOMTVE GRD SYNCHRN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet