13
AT45DB011B
1984J–DFLASH–06/06
Note: 1. I
cc1
during a buffer read is 20mA maximum.
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
SB
Standby Current CS, RESET, WP = V
IH
, all inputs at
CMOS levels
210µA
I
CC1
(1)
Active Current, Read Operation f = 20 MHz; I
OUT
= 0 mA; V
CC
= 3.6V 4 10 mA
I
CC2
Active Current, Program/Erase
Operation
V
CC
= 3.6V 10 25 mA
I
LI
Input Load Current V
IN
= CMOS levels 1 µA
I
LO
Output Leakage Current V
I/O
= CMOS levels 1 µA
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 1.6 mA; V
CC
= 2.7V 0.4 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
- 0.2V V
AC Characteristics
Symbol Parameter Min Typ Max Units
f
SCK
SCK Frequency 20 MHz
f
CAR
SCK Frequency for Continuous Array Read 20 MHz
t
WH
SCK High Time 22 ns
t
WL
SCK Low Time 22 ns
t
CS
Minimum CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
t
CSB
CS High to RDY/BUSY Low 200 ns
t
SU
Data In Setup Time 5 ns
t
H
Data In Hold Time 10 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 18 ns
t
V
Output Valid 20 ns
t
XFR
Page to Buffer Transfer/Compare Time 120 200 µs
t
EP
Page Erase and Programming Time 10 20 ms
t
P
Page Programming Time 715ms
t
PE
Page Erase Time 610ms
t
BE
Block Erase Time 715ms
t
RST
RESET Pulse Width 10 µs
t
REC
RESET Recovery Time s
14
AT45DB011B
1984J–DFLASH–06/06
Input Test Waveforms and Measurement Levels
t
R
, t
F
< 3 ns (10% to 90%)
Output Test Load
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS
makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS
makes a high-to-low transition. Both waveforms show valid timing diagrams. The
setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK
signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows
timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WH
t
WL
t
CSH
t
CS
t
V
HIGH IMPEDANCE
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
15
AT45DB011B
1984J–DFLASH–06/06
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (Except Status Register Read)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
t
RST
t
REC
t
CSS
SI CMD 8 bits
8 bits
8 bits
MSB
Reserved for
larger densities
Page Address
(PA8-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
LSBr r r r r r X X X X X X X X X X X X X X X X X X

AT45DB011B-XU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 1M SERIAL 2.7V - IND TEMP
Lifecycle:
New from this manufacturer.
Delivery:
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