7
AT45DB011B
1984J–DFLASH–06/06
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of
the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations.
Data is first shifted into the buffer from the SI pin and then programmed into a specified page
in the main memory. An 8-bit opcode of 82H is followed by the six reserved bits and 18
address bits. The nine most significant address bits (PA8-PA0) select the page in the main
memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the
first byte in the buffer to be written. After all address bits are shifted in, the part will take data
from the SI pin and store it in the data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the
CS
pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and should take place in a maximum of
time t
EP
. During this time, the status register will indicate that the part is busy.
Additional
Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the
main memory to buffer. An 8-bit opcode of 53H is followed by the six reserved bits, nine
address bits (PA8-PA0) which specify the page in main memory that is to be transferred, and
nine don’t care bits. The CS
pin must be low while toggling the SCK pin to load the opcode,
the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from
the main memory to the buffer will begin when the CS
pin transitions from a low to a high state.
During the transfer of a page of data (t
XFR
), the status register can be read to determine
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be com-
pared to the data in the buffer. An 8-bit opcode of 60H is followed by 24 address bits
consisting of the six reserved bits, nine address bits (PA8-PA0) which specify the page in the
main memory that is to be compared to the buffer, and nine don’t care bits. The loading of the
opcode and the address bits is the same as described previously. The CS
pin must be low
while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from
the SI pin. On the low-to-high transition of the CS
pin, the 264 bytes in the selected main mem-
ory page will be compared with the 264 bytes in the buffer. During this time (t
XFR
), the status
register will indicate that the part is busy. On completion of the compare operation, bit 6 of the
status register is updated with the result of the compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple
pages of data are modified in a random fashion. This mode is a combination of two operations:
Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in
Erase. A page of data is first transferred from the main memory to the data buffer, and then the
same data (from the buffer) is programmed back into its original page of main memory. An 8-
bit opcode of 58H is followed by the six reserved bits, nine address bits (PA8-PA0) that spec-
ify the page in main memory to be rewritten, and nine additional don’t care bits. When a low-
to-high transition occurs on the CS
pin, the part will first transfer data from the page in main
memory to the buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of t
EP
.
During this time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 2 on page 27 is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program opera-
tions in that sector.
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AT45DB011B
1984J–DFLASH–06/06
Note: 1. After power is applied and V
CC
is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
DC and AC Operating Range
AT45DB011B
Operating Temperature (Case)
Com. 0°C to 70°C
Ind. -40°C to 85°C
V
CC
Power Supply
(1)
2.7V to 3.6V
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AT45DB011B
1984J–DFLASH–06/06
Operation Mode
Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array
(Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer Transfer
3. Main Memory Page to Buffer Compare
4. Buffer to Main Memory Page Program with Built-in Erase
5. Buffer to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer Read
2. Buffer Write
3. Status Register Read
If a Group A mode is in progress (not fully completed), then another mode in Group A should
not be started. However, during this time in which a Group A mode is in progress (other than
Main Memory Page Read), Status Register Read from Group B can be started. Furthermore,
during Page Erase and Block Erase operation in progress from Group A, any of the modes
from Group B can be started.
Pin Descriptions SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the device.
The SI pin is used for all data input, including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out from the
device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow of
data to and from the DataFlash. Data is always clocked into the device on the rising edge of
SCK and clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS
): The DataFlash is selected when the CS pin is low. When the device is
not selected, data will not be accepted on the SI pin, and the SO pin will remain in a high-
impedance state. A high-to-low transition on the CS
pin is required to start an operation, and a
low-to-high transition on the CS
pin is required to end an operation.
WRITE PROTECT: If the WP
pin is held low, the first 256 pages of the main memory cannot
be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect
pin high and then use the program commands previously mentioned. If this pin and feature are
not utilized it is recommended that the WP
pin be driven high externally.

AT45DB011B-XU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 1M SERIAL 2.7V - IND TEMP
Lifecycle:
New from this manufacturer.
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