MC100EP196
http://onsemi.com
10
Table 10. DC CHARACTERISTICS, NECL V
CC
= 0 V, V
EE
= −3.3 V (Note 5)
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 100 125 160 110 130 170 110 135 175 mA
V
OH
Output HIGH Voltage (Note 6) −1145 −1000 −895 −1145 −1000 −895 −1145 −1000 −895 mV
V
OL
Output LOW Voltage (Note 6) −1995 −1780 −1695 −1995 −1800 −1695 −1995 −1815 −1695 mV
V
IH
Input HIGH Voltage (Single−Ended)
LVNECL
−1225 −880 −1225 −880 −1225 −880
mV
V
IL
Input LOW Voltage (Single−Ended)
LVNECL
−1995 −1625 −1995 −1625 −1995 −1625
mV
V
BB
Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
V
EF
Reference Voltage for ECL Mode
Connection
−1400 −1340 −1250 −1425 −1347 −1250 −1450 −1355 −1250 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
V
EE
+2.0 0 V
EE
+2.0 0 V
EE
+2.0 0 V
I
IH
Input HIGH Current
IN, IN
, EN, LEN, SETMIN, SETMAX 150 150 150
mA
I
IHH
FTUNE Input High Current @ V
CC
50 87 150 50 84 150 50 82 150
mA
I
IL
Input LOW Current
IN, IN
, EN, LEN, SETMIN, SETMAX 0.5 0.5 0.5
mA
I
ILL
FTUNE Input LOW Current @ V
EE
−10 0 10 −10 0 10 −10 0 10
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to −0.3 V.
6. All loading with 50 W to V
CC
− 2.0 V.
7. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
MC100EP196
http://onsemi.com
11
Table 11. AC CHARACTERISTICS V
CC
= 0 V; V
EE
= −3.0 V to −3.6 V or V
CC
= 3.0 V to 3.6 V; V
EE
= 0 V (Note 8)
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Frequency 1.2 1.2 1.2 GHz
t
PLH
t
PHL
Propagation Delay
IN to Q; D(0−9) = 0
IN to Q; D(0−9) = 1023
EN
to Q; D(0−9) = 0
D10 to CASCADE
1810
9500
1780
350
2210
11496
2277
450
2610
13500
2780
550
1960
10000
1930
380
2360
12258
2430
477
2760
14000
2930
580
2180
10955
2150
420
2580
13454
2650
520
2980
15955
3150
620
ps
t
RANGE
Programmable Range
{D(0−9) = HI} − {D(0−9) = LO}
8600 9285 10000 9200 9897 10700 9900 10875 12000
ps
Dt
Step Delay (Note 9)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
90
245
530
1060
2160
4335
7
23
39
58
137
293
590
1158
2317
4647
185
335
650
1265
2490
5010
100
260
560
1130
2290
4590
11
30
48
67
149
313
629
1237
2472
4955
200
370
710
1355
2680
5385
90
270
600
1200
2450
4935
13
32
53
73
154
337
681
1353
2712
5440
225
410
770
1520
3015
6015
ps
Mono Monotonicity (Note 10) ps
t
SKEW
Duty Cycle Skew (Note 11)
|t
PHL
−t
PLH
| 20 22 27
ps
t
s
Setup Time
D to LEN
D to IN (Note 12)
EN
to IN (Note 13)
150
100
150
−10
−130
−105
150
100
150
−70
−150
−120
150
100
150
−70
−165
−140
ps
t
h
Hold Time
LEN to D
IN to EN
(Note 14)
225
450
170
275
200
450
70
305
200
450
60
325
ps
t
R
Release Time
EN
to IN (Note 15)
SET MAX to LEN
SET MIN to LEN
150
400
300
−105
70
165
150
400
350
−120
110
180
150
400
350
−140
160
205
ps
t
jit
Random Clock Jitter
@ 1.2 GHz, SETMAX Delay
3 3 3 ps
V
PP
Input Voltage Swing
(Differential Configuration)
150 800 1200 150 800 1200 150 800 1200 mV
t
r
t
f
Output Rise/Fall Time
20−80% (Q)
20−80% (CASCADE)
85
100
110
150
130
200
95
110
120
160
145
210
110
125
135
175
160
225
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V.
9. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
10.The monotonicity indicates the increased delay value for each binary count increment on the control inputs D(0−9).
11. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
12.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
13.This setup time is the minimum time that EN
must be asserted prior to the next transition of IN/IN to prevent an output response greater than
V
CC
− 1425 mV to that IN/IN transition.
14.This hold time is the minimum time that EN
must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than V
CC
− 1425 mV to that IN/IN transition.
15.This release time is the minimum time that EN
must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
MC100EP196
http://onsemi.com
12
Figure 4. AC Reference Measurement
IN
IN
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) − V
IL
(D)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
Using the FTUNE Analog Input
The analog FTUNE pin on the EP196 device is intended
to add more delay in a tunable gate to enhance the 10 ps
resolution capabilities of the fully digital EP196. The level
of resolution obtained is dependent on the voltage applied to
the FTUNE pin.
To provide this further level of resolution, the FTUNE pin
must be capable of adjusting the additional delay finer than
the 10 ps digital resolution (See Logic Diagram). This
requirement is easily achieved because a 60 ps additional
delay can be obtained over the entire FTUNE voltage range
(See Figure 5). This extra analog range ensures that the
FTUNE pin will be capable even under worst case
conditions of covering a digital resolution. Typically, the
analog input will be driven by an external DAC to provide
a digital control with very fine analog output steps. The final
resolution of the device will be dependent on the width of the
DAC chosen.
To determine the voltage range necessary for the FTUNE
input, Figure 5 should be used. There are numerous voltage
ranges which can be used to cover a given delay range; users
are given the flexibility to determine which one best fits their
designs.
Figure 5. Typical EP196 Delay versus FTUNE Voltage
FTUNE VOLTAGE (V)
−3.3 −2.97 −2.64 −2.31 −1.98 −1.65 −1.32 −0.99 −0.66 −0.33 0
90
80
70
60
50
40
30
20
10
0
−10
DELAY (ps)
−40°C
85°C
25°C
V
CC
= 0 V
V
EE
= −3.3 V
V
CC
V
EE

MC100EP196FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Delay Lines / Timing Elements 3.3V/5V ECL Programmable Delay
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet