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MC100EP196FAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MC100EP196
http://onsemi.com
16
Multi−Channel Deskewing
The most practical application for EP196 is in multiple
channel delay matching. Slight differences in impedance
and cable length can create large timing skews within a
high−speed system. To deskew multiple signal channels,
each channel can be sent through each EP196 as shown in
Figure 8. One signal channel can be used as reference and the
other EP196s can be used to adjust the delay to eliminate the
timing skews. Nearly any high−speed system can be fine
tuned (as small as 10 ps) to reduce the skew to extremely
tight tolerances using the available FTUNE pin.
Figure 8. Multiple Channel Deskewing Diagram
EP196
IN Q
IN
Q
#1
EP196
IN Q
IN
Q
#2
EP196
IN Q
IN Q
#N
Digital
Data
Control
Logic
DAC
MC100EP196
http://onsemi.com
17
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
− 2.0 V
ORDERING INFORMATION
Device Package Shipping
†
MC100EP196FAG LQFP−32
(Pb−Free)
250 Units / Tray
MC100EP196FAR2G LQFP−32
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
MC100EP196
http://onsemi.com
18
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q
_
W
K
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1
V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) ZAC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M
_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B 7.000 BSC 0.276 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.450 0.750 0.018 0.030
M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
___ _
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MC100EP196FAG

Mfr. #:
Buy MC100EP196FAG
Manufacturer:
ON Semiconductor
Description:
Delay Lines / Timing Elements 3.3V/5V ECL Programmable Delay
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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