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CS4353-CZZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
http://www.cirrus.com
3.3 V Stereo Audio DAC with 2 V
RMS
Line Output
Features
Multi-bit Delta-Sigma Modulator
106 dB A-wt Dynamic Range
-93 dB THD+N
Single-ended Ground Centered Analog
Architecture
– No DC-blocking Capacitors Required
– Integrated Step-up/Inverting Charge Pump
– Filtered Line-level Outputs
– Selectable 1 or 2 V
RMS
Full-scale Output
Low Clock-jitter Sensitivity
Low-latency Digital Filtering
Supports Sample Rates up to 192 kHz
24-bit Resolution
+3.3 V Charge Pump and Core Logic, +3.3 V
Analog, and +0.9 to 3.3 V Interface Power
Supplies
Low Power Consumption
24-pin QFN, Lead-free Assembly
Description
The CS4353 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-em-
phasis, analog filtering, and on-chip 2 V
RMS
line-level
driver from a 3.3 V supply.
The advantages of this architecture include ideal differ-
ential linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temper-
ature, high tolerance to clock jitter, and a minimal set of
external components.
The CS4353 is available in a 24-pin QFN package in
Commercial (-40°C to +85°C) grade. The CDB4353
Customer Demonstration Board is also available for de-
vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 25 for com-
plete details.
These features are ideal for cost-sensitive, 2-channel
audio systems including video game consoles, DVD
players and recorders, A/V receivers, set-top boxes,
digital TVs, mini-component systems, and mixing
consoles.
PCM Serial
Audio Port
Level Shifter
Serial
Audio
Input
Multibit
ΔΣ Modulator
Interpolation
Filters
Digital Core Logic and
Charge Pump Supply (VCP)
+3.3 V
Left Channel
Right Channel
Hardware
Control
Power-On
Reset
Hardware
Control
Reset
Auto Speed
Mode Detect
Analog Supply (VA)
+3.3 V
Inverting
Step-Up
+VA_H
-VA_H
Interface Supply (VL)
+0.9 V to +3.3 V
Ground-Centered,
2 Vrms Line Level Outputs
DAC
Pseudo Diff. Input
JUN '09
DS803F1
CS4353
2 DS803F1
CS4353
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................. 4
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DAC ANALOG CHARACTERISTICS .................................................................................................... 7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 8
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................................... 9
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10
INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12
4. APPLICATIONS ................................................................................................................................... 13
4.1.1 Ground-centered Outputs ...................................................................................................... 13
4.1.2 Full-scale Output Amplitude Control ......................................................................................13
4.1.3 Pseudo-differential Outputs ................................................................................................... 13
4.9.1 Power-up Sequences ............................................................................................................ 19
4.9.1.1 External RESET Power-up Sequence ....................................................................... 19
4.9.1.2 Internal Power-on Reset Power-up Sequence .......................................................... 19
4.9.2 Power-down Sequences ....................................................................................................... 19
4.9.2.1 External RESET Power-down Sequence .................................................................. 19
4.9.2.2 Internal Power-on Reset Power-down Sequence ...................................................... 19
4.10.1 Capacitor Placement ........................................................................................................... 20
5. DIGITAL FILTER RESPONSE PLOTS ................................................................................................ 21
6. PARAMETER DEFINITIONS ................................................................................................................ 23
7. PACKAGE DIMENSIONS .................................................................................................................... 24
8. ORDERING INFORMATION ................................................................................................................ 25
9. REVISION HISTORY ............................................................................................................................ 25
DS803F1 3
CS4353
LIST OF FIGURES
Figure 1.Serial Input Timing ........................................................................................................................ 9
Figure 2.Power-on Reset Threshold Sequence ........................................................................................ 10
Figure 3.Typical Connection Diagram ....................................................................................................... 12
Figure 4.Stereo Pseudo-differential Output ............................................................................................... 13
Figure 5.I²S, up to 24-bit Data ................................................................................................................... 15
Figure 6.Left-justified up to 24-bit Data ..................................................................................................... 15
Figure 7.De-emphasis Curve, Fs = 44.1 kHz ............................................................................................ 16
Figure 8.Internal Power-on Reset Circuit .................................................................................................. 16
Figure 9.Initialization and Power-down Sequence Diagram ..................................................................... 18
Figure 10.Single-speed Stopband Rejection ............................................................................................. 21
Figure 11.Single-speed Transition Band ................................................................................................... 21
Figure 12.Single-speed Transition Band (detail) ....................................................................................... 21
Figure 13.Single-speed Passband Ripple ................................................................................................. 21
Figure 14.Double-speed Stopband Rejection ........................................................................................... 21
Figure 15.Double-speed Transition Band ................................................................................................. 21
Figure 16.Double-speed Transition Band (detail) ..................................................................................... 22
Figure 17.Double-speed Passband Ripple ............................................................................................... 22
Figure 18.Quad-speed Stopband Rejection .............................................................................................. 22
Figure 19.Quad-speed Transition Band .................................................................................................... 22
Figure 20.Quad-speed Transition Band (detail) ........................................................................................ 22
Figure 21.Quad-speed Passband Ripple .................................................................................................. 22
LIST OF TABLES
Table 1. Digital I/O Pin Characteristics ..................................................................................................... 11
Table 2. CS4353 Operational Mode Auto-Detect ...................................................................................... 14
Table 3. Single-speed Mode Standard Frequencies ................................................................................. 14
Table 4. Double-speed Mode Standard Frequencies ............................................................................... 14
Table 5. Quad-speed Mode Standard Frequencies ..................................................................................14
Table 6. Digital Interface Format ............................................................................................................... 15
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

CS4353-CZZ

Mfr. #:
Buy CS4353-CZZ
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs 3.3V Stereo DAC w/ 2Vrms Line Driver
Lifecycle:
New from this manufacturer.
Delivery:
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