© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
1 Publication Order Number:
NB3N401S/D
NB3N401S
3.3 V Quad Channel
Half‐Duplex M-LVDS
Driver Receiver
Description
The NB3N401S is a 3.3 V supply Quad Multipoint Low Voltage
Differential Signals (M−LVDS) line drivers and receivers. The device
is TIA/EIA−899 compliant. The device offers the Type 1 receiver
threshold at 0.0 V and the Type 2 receiver threshold at 0.1 V.
The NB3N401S supports four independent Half Duplex bus
configurations.
Each of the four sections has Pin (SEL) for selection of Type−1 and
Type−2 receivers that detect the bus state with as little as 50 mV of
differential input voltage over a common mode voltage range of −1 V
to 3.4 V. The Type−1 receivers have near zero thresholds (±50 mV)
and exhibit 25 mV of differential input voltage hysteresis to prevent
output oscillations with slowly changing signals or loss of input.
Type−2 receivers include an offset threshold to provide a detectable
voltage under open-circuit, idle-bus, and other faults conditions.
The NB3N401S is offered in a 48 Pin 7 mm × 7mm × 0.9 mm QFN
package.
Features
• Low-Voltage Differential 30 to 55 W Line Drivers and Receivers for
Signaling Rates Up to 250 Mbps
• Clock Frequencies up to 125 MHz
• Type−1 Receivers Incorporate 25 mV of Hysteresis
• Type−2 Receivers Provide an Offset (100 mV)
• Compatible with TIA/EIA−899 Standard for Multipoint Data
Interchange
• Controlled Driver Output Voltage Transition Times for Improved
Signal Quality
• −1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer
With up to 2 V of Ground Noise
• Bus Pins High Impedance when Disabled or V
CC
≤ 1.5 V
• Independent Enable for each Driver and Receiver
• Independent Select for each Type1 and Type2 Receivers
• M−LVDS Bus Power Up/Down Glitch Free
• Power Down Pin for Device Power Down
• Operating Range: V
CC
= 3.3 V ±0.3 V (3.0 to 3.6 V)
• Operation from –40°C to 85°C.
• Enhanced ESD Protection: 7 kV HBM on all the Pins
• These are Pb-Free Devices
Applications
• Mobile Base Station Back Plane System
• Central Office Switches
• Network Switches
MARKING DIAGRAM
www.
onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
QFN48
CASE 485EP
NB3N401S = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
LOGIC DIAGRAM
A1
B1
A2−A4
B2−B4
DE1
D1
SEL1
R1
RE1
PDN
DE2−DE4
D2−D4
RE2−RE4
R2−R4
SEL2−SEL4
Channel 1
Channel 2−4
148
NB3N401S
AWLYYWWG
1
