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Table 7. ELECTRICAL CHARACTERISTICS (V
CC
= 3.3 V ±0.3 V, GND = 0 V, T
A
−40°C to +85°C) (continued)
Symbol UnitMaxTypMinTest ConditionsParameter
RECEIVER SWITCHING
t
pLH
Propagation Delay time, Low to High
Level Output
C
L
= 15 pF (Figure 12) 2.5 4.5 6.4 ns
t
pHL
Propagation Delay time, High to Low
Level Output
C
L
= 15 pF (Figure 12) 2.5 4.5 6.4 ns
t
r
Output Signal Rise Time C
L
= 15 pF (Figure 12) 1.4 2.65 ns
t
f
Output Signal Fall Time C
L
= 15 pF (Figure 12) 1.15 2.35 ns
t
SK(o)
Output Skew C
L
= 15 pF (Figure 12) 350 ps
t
SK(pp)
Pulse Skew (|t
PHL
− t
PLH
|)
Type 1
Type 2
C
L
= 15 pF (Figure 12)
35
150
210
700
ps
t
SK(pp)
Device to Device Skew (Note 2) C
L
= 15 pF (Figure 12) 800 ps
T
JIT(per)
Periodic Jitter RMS
(1 Standard Deviation) (Note 1)
125 MHz Clock Input, t
r
= t
f
= 0.5 ns
(10% to 90%), Switching on All Channels
(Figure 13)
6 ps
T
JIT(cc)
Cycle to Cycle Jitter RMS (Note 1) 125 MHz Clock Input, t
r
= t
f
= 0.5 ns
(10% to 90%), Switching on All Channels
(Figure 13)
13 ps
T
JIT(det)
Deterministic Jitter (Note 1)
Type 1
Type 2
Switching on All Channels, 250 Mbps 2
15
−1
PRBS Input, t
r
= t
f
= 0.5 ns (10% to 90%)
(Figure 13)
800
945
ps
T
JIT(r)
Random Jitter (Note 1)
Type 1
Type 2
Switching on All Channels, 250 Mbps 2
15
−1
PRBS Input, t
r
= t
f
= 0.5 ns (10% to 90%)
(Figure 13)
90
65
ps
t
pZH
Enable Time, High Impedance to High
Level Output
C
L
= 15 pF (Figure 14) 15 ns
t
pZL
Enable Time, High Impedance to Low
Level Output
C
L
= 15 pF (Figure 14) 15 ns
t
pHZ
Disable Time, High Level to High
Impedance Output
C
L
= 15 pF (Figure 14) 10 ns
t
pLZ
Disable Time, Low Level to High
Impedance Output
C
L
= 15 pF (Figure 14) 10 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Jitter is ensured by Design and characterization
2. t
SK(pp)
is the amplitude of the difference in propagation delay time between any specified terminals of two Devices that operates with same
Power Supply Voltage, test circuits at same temperature and having identical packages.
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Figure 3. Receiver Voltage and Current Definitions
I
B
I
O
V
ID
V
B
B
R
A
V
A
V
O
I
A
V
CM
(V
A
+ V
B
) / 2
Table 8. TYPE 1 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages Resulting Differential Input Voltage Resulting Common Mode Input Voltage
Receiver
Output
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.400 3.365 0.035 3.3825 H
3.365 3.400 –0.035 3.3825 L
–0.965 –1.000 0.035 –0.9825 H
–1.000 –0.965 –0.035 –0.9825 L
*H = High Level, L = Low Level, Output State assumes Receiver is Enabled (RE = L)
Table 9. TYPE 2 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages Resulting Differential Input Voltage Resulting Common Mode Input Voltage
Receiver
Output
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.400 3.25 0.150 3.325 H
3.400 3.35 0.050 3.375 L
–0.850 –1.000 0.150 –0.925 H
–0.950 –1.000 0.050 –0.975 L
*H = High Level, L = Low Level, Output State assumes Receiver is Enabled (RE = L)
Figure 4. Driver Voltage and Current Definitions
V
CC
I
I
I
A
I
B
V
I
V
A
V
AB
V
B
V
OS
B
D
A
(V
A
+ V
B
) / 2
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9
Figure 5. Differential Output Voltage Test Circuit
+
V
AB
B
D
A
3.32 kW
3.32 kW
49.9 W
−1 V V
test
3.4 V
Figure 6. Driver Short-Circuit Test Circuit
I
OS
B
A
−1 V or 3.4 V
+
V
test
0 V or V
CC
Figure 7. Maximum Steady State Output Voltage
V
A
or V
B
B
A
1.62 kW ±1%
0 V or V
CC
Figure 8. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
V
OS
B
D
A
R1
24.9 W
C3
2.5 pF
C2
1 pF
C1
1 pF
R2
24.9 W
V
OS
V
OS(PP)
V
OS(SS)
B
A
~1.3 V
~0.7 V
Notes:
1. All Input pulses are supplied by a Generator having characteristics as follows: t
r
or t
f
1 ns, pulse frequency = 1 MHz & Duty cycle = 50 ±5%.
2. Capacitor values indicated is inclusive of fixture and instrumentation Capacitance with 20 mm of the D.U.T. and are ±20%.
3. All Resistors are metal Film, Surface Mount, ±1% and located within 20 mm of the D.U.T.
4. The measurement of V
OS(pp)
is made on Test equipment with a –3 dB Bandwidth of at least 1 GHz.

NB3N401SMNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LVDS Interface IC 3.3 V QUAD CHANNEL HALFDU
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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