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NB3N401SMNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15
NB3N401S
www.onsemi.com
4
Table 3. ATTRIBUTES (Note 1)
Characteristics
Value
ESD Protection
Human Body Model (JEDEC Standard JS−001−2014) All Pins ±7 kV
Charged Device Model (JEDEC Standard 22, Method C101−D) All Pins ±1500 V
Moisture Sensitivity (Note 1) Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL−94 Code V−0 A 1/8″
28 to 34
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latch-Up Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 1)
Symbol Parameter Condition Rating Unit
V
CC
Supply Voltage −0.5 ≤ V
CC
≤ 4.0 V
V
IN
Input Voltage D, DE, RE, SEL
A, B
−0.5 ≤ V
IN
≤ 4.0
−1.8 ≤ V
IN
≤ 4.0
V
V
OUT
Output Voltage R
A or B
−0.3 ≤ V
OUT
≤ 4.0
−1.8 ≤ V
OUT
≤ 4.0
V
T
A
Operating Temperature Range, Industrial −40 to +85 °C
T
J
Maximum Junction Temperature 140 °C
T
STG
Storage Temperature Range −65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
Table 5. THERMAL CHARACTERISTICS
Symbol Parameter Condition Rating Unit
θ
JP
Thermal Resistance (Junction-to-Pad) (Note 2) 1.5 (Typ) °C/W
θ
JC
Thermal Resistance (Junction-to-Case) (Note 2) 16 (Typ) °C/W
θ
JB
Thermal Resistance (Junction-to-Board) (Note 2) 11 (Typ) °C/W
P
D
Power Dissipation RE = 0 V, DE = 0 V, CL = 15 pF,
VID = 400 mV, 125 MHz,
All Other Pins Open
382 (Max) mW
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS (V
CC
= 3.3 V ±0.3 V, GND = 0 V, T
A
−40°C TO +85°C)
Symbol
Parameter Test Conditions Min Typ Max Unit
I
CC
Power
Supply
Curren
t
Driver Only Receiver Disabled, Driver Enabled, RE and DE
at V
CC
, R
L
= 50 W, 125 MHz, All Others Open,
PDN = High
76
mA
Both Driver and Receiver
Disabled
Driver and Receiver Disabled, RE at V
CC
,
DE at 0 V, R
L
= No Load, 125 MHz, All Others
Open, PDN = High
10
Both Driver and Receiver
Enabled
Driver and Receiver Enabled, RE at 0 V,
DE at V
CC
, R
L
= 50 W, C
L
= 15 pF, 125 MHz,
All Others Open, PDN = High
165
Receiver Only Receiver Enabled, Driver Disabled, RE and
DE at 0 V, R
L
= 50 W, C
L
= 15 pF, 125 MHz,
All Others Open, PDN = High
100
PDN Power Down (PDN = L) − − 5 mA
V
IH
Input HIGH Voltage 2 − VCC V
V
IL
Input LOW Voltage GND − 0.8 V
V
BUS
Voltage at any Bus Terminal VA. VB −1.4 − 3.8 V
|VID| Magnitude of Differential Input Voltage 0.05 − VCC V
NB3N401S
www.onsemi.com
5
Table 7. ELECTRICAL CHARACTERISTICS (V
CC
= 3.3 V ±0.3 V, GND = 0 V, T
A
−40°C to +85°C)
Symbol
Parameter Test Conditions Min Typ Max Unit
BUS INPUT AND OUTPUT
I
A
Receiver or Transceiver with Driver
Disabled Input Current
V
A
= 3.8 V, V
B
= 1.2 V
V
A
= −1.4 V, V
B
= 1.2 V
−
−32
−
−
32
−
mA
I
B
Receiver or Transceiver with Driver
Disabled Input Current
V
B
= 3.8 V, V
A
= 1.2 V
V
B
= −1.4 V, V
A
= 1.2 V
−
−32
−
−
32
−
mA
I
AB
Receiver or Transceiver with Driver
Disabled Differential Input Current
(I
A
– I
B
)
V
A
= V
B
, −1.4 V ≤ V
A
≤ 3.8 V −4 − 4
mA
I
AOFF
Receiver or Transceiver Power-Off Input
Current
V
A
= 3.8 V, V
B
= 1.2 V, 0 V ≤ V
CC
≤ 1.5 V
V
A
= −1.4 V, V
B
= 1.2V, 0 V ≤ V
CC
≤ 1.5 V
−
−32
−
−
32
−
mA
I
BOFF
Receiver or Transceiver Power-Off Input
Current
V
B
= 3.8 V, V
A
= 1.2V, 0 V ≤ V
CC
≤ 1.5 V
V
B
= −1.4 V, V
A
= 1.2V, 0 V ≤ V
CC
≤ 1.5 V
−
−32
−
−
32
−
mA
I
ABOFF
Receiver or Transceiver Power-Off
Differential Input Current (I
AOFF
– I
BOFF
)
V
A
= V
B
, 0 V ≤ V
CC
≤ 1.5 V,
−1.4 V ≤ V
A
≤ 3.8 V
−4 − 4
mA
C
A
Transceiver with Driver Disabled Input
Capacitance
V
A
= 0.4 sin (30e
6
p
t
) + 0.5 V, V
B
= 1.2 V
− 5 − pF
C
B
Transceiver with Driver Disabled Input
Capacitance
V
B
= 0.4 sin (30e
6
p
t
) + 0.5 V, V
A
= 1.2 V
− 5 − pF
C
AB
Transceiver with Driver Disabled
Differential Input Capacitance
V
AB
= 0.4 sin (30e
6
p
t
)
− − 3 pF
C
A/B
Transceiver with Driver Disabled Input
Capacitance Balance (C
A
/C
B
)
0.99 − 1.01
DRIVER
|V
AB
| Differential Output Voltage Amplitude
(A, B)
(Figure 5) 480 − 650 mV
D|V
AB
|
Change in Differential Output Voltage
Amplitude between Logic states (A, B)
(Figure 5) −50 − 50 mV
V
OS(SS)
Steady State Common Mode Output
Voltage (A, B)
(Figure 8) 0.7 − 1.1 V
DV
OS(SS)
Change in Steady state Common Mode
Output Voltage between Logic states
(A, B)
(Figure 8) −50 − 50 mV
V
OS(PP)
Peak to Peak Common Mode Output
Voltage (A, B)
(Figure 8) − − 150 mV
V
AOC
Maximum Steady State Open Circuit
Output Voltage (A, B)
(Figure 7) 0 − 2.4 V
V
BOC
Maximum Steady State Open Circuit
Output Voltage (A, B)
(Figure 7) 0 − 2.4 V
V
P(H)
Voltage Overshoot Low to High Level
Output (A, B)
(Figure 9) − − 1.2V
SS
V
V
P(L)
Voltage Overshoot High to Low Level
Output (A, B)
(Figure 9) −0.2V
SS
− − V
I
IH
High Level Input Current (D, DE) V
IH
= 2 V to V
CC
− − 10
mA
I
IL
Low Level Input Current (D, DE) V
IL
= GND to 0.8 V − − 10
mA
|I
OS
| Differential Short Circuit Output Current
Amplitude (A, B)
(Figure 6) − − 24 mA
C
I
Input Capacitance (D, DE)
V
I
= 0.4 sin (30e
6
p
t
) + 0.5 V
− 5 − pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
External DC Source when used for measurement to have low Ripple/Noise at board input.
NB3N401S
www.onsemi.com
6
Table 7. ELECTRICAL CHARACTERISTICS (V
CC
= 3.3 V ±0.3 V, GND = 0 V, T
A
−40°C to +85°C) (continued)
Symbol UnitMaxTypMinTest ConditionsParameter
RECEIVER
V
IT+
+ve Going Differential Input Voltage
Threshold (A,B)
Type 1 (Table 8)
Type 2 (Table 9)
−
−
−
−
35
150
mV
V
IT−
−ve Going Differential Input Voltage
Threshold (A,B)
Type 1 (Table 8)
Type 2 (Table 9)
−35
50
−
−
−
−
mV
V
HYS
Differential Input Voltage Hysteresis
[VIT+ − VIT−] (A,B)
Type 1 (Table 8)
Type 2 (Table 9)
−
−
25
0
−
−
mV
V
OH
High Level Output Voltage (R) I
OH
= −8 mA 2.4 − − V
V
OL
Low Level Output Voltage (R) I
OL
= 8 mA − − 0.4 V
I
IH
High Level Input Current (RE) V
IH
= 2 V to V
CC
−10 − −
mA
I
IL
Low Level Input Current (RE) V
IL
= GND to 0.8 V −10 − −
mA
I
OZ
High Impedance Output Current (R) V
O
= 0 V or V
CC
−10 − 15
mA
External DC Source when used for measurement to have low Ripple/Noise at board input.
DRIVER SWITCHING
t
pLH
Propagation Delay time, Low to High
Level Output
(Figure 9) 1.3 1.9 2.4 ns
t
pHL
Propagation Delay time, High to Low
Level Output
(Figure 9) 1.3 1.9 2.4 ns
t
r
Differential Output Signal Rise Time (Figure 9) 0.9 − 2 ns
t
f
Differential Output Signal Fall Time (Figure 9) 0.9 − 2.2 ns
t
SK(o)
Output Skew (Figure 9) − − 200 ps
t
SK(pp)
Pulse skew ⎮t
PHL
− t
PLH
⎜ (Figure 9) − − 150 ps
t
SK(pp)
Device to Device Skew (Note 2) (Figure 9) − − 300 ps
T
JIT(per)
Periodic Jitter RMS (1 Standard deviation)
(Note 1)
125 MHz Clock Input, t
r
= t
f
= 0.5 ns (10%
to 90%), Switching on All Channels
(Figure 10)
− − 2 ps
T
JIT(cc)
Cycle to Cycle Jitter RMS
(Note 1)
125 MHz Clock Input, t
r
= t
f
= 0.5 ns (10%
to 90%), Switching on All Channels
(Figure 10)
− − 9 ps
T
JIT(det)
Deterministic Jitter
(Note 1)
Switching on All Channels, 250 Mbps 2
15
−1
PRBS Input, t
r
= t
f
= 0.5 ns (10% to 90%)
(Figure 10)
− − 290 ps
T
JIT(r)
Random Jitter
(Note 1)
Switching on All Channels, 250 Mbps 2
15
−1
PRBS Input, t
r
= t
f
= 0.5 ns (10% to 90%)
(Figure 10)
− − 16 ps
t
pZH
Enable Time, High Impedance to High
Level Output
(Figure 11) − − 7 ns
t
pZL
Enable Time, High Impedance to Low
Level Output
(Figure 11) − − 7 ns
t
pHZ
Disable Time, High Level to High
Impedance Output
(Figure 11) − − 7 ns
t
pLZ
Disable Time, Low Level to High
Impedance Output
(Figure 11) − − 7 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Jitter is ensured by Design and characterization
2. t
SK(pp)
is the amplitude of the difference in propagation delay time between any specified terminals of two Devices that operates with same
Power Supply Voltage, test circuits at same temperature and having identical packages.
P1-P3P4-P6P7-P9P10-P12P13-P15

NB3N401SMNTXG

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Manufacturer:
ON Semiconductor
Description:
LVDS Interface IC 3.3 V QUAD CHANNEL HALFDU
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