LTC3731
13
3731fc
(Refer to Functional Diagram)
OPERATION
APPLICATIONS INFORMATION
capacitor, the controller will be shut down until the RUN/
SS pin voltage is recycled. This built-in latchoff can be
overridden by providing >5µA at a compliance of 3.8V
to the RUN/SS pin. This additional current shortens the
soft-start period but prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled. Foldback
current limit can be overridden by clamping the EAIN pin
such that the voltage is held above the (70%)(0.6V) or
0.42V level even when the actual output voltage is low. Up
to 100µA of input current can safely be accommodated
by the RUN/SS pin.
Input Undervoltage Reset
The RUN/SS capacitor will be reset if the input voltage
(V
CC
) is allowed to fall below approximately 4V. The
capacitor on the RUN/SS pin will be discharged until
the short-circuit arming latch is disarmed. The RUN/SS
capacitor will attempt to cycle through a normal soft-start
ramp up after the V
CC
supply rises above 4V. This circuit
prevents power supply latchoff in the event of input power
switching break-before-make situations. The PGOOD pin
is held low during start-up until the RUN/SS capacitor
rises above the short-circuit latchoff arming threshold of
approximately 3.8V.
The basic application circuit is shown in Figure 1 on the
first page of this data sheet. External component selection
is driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltage ripple requirements. Once the inductors and op-
erating frequency have been chosen, the current sensing
resistors can be calculated. Next, the power MOSFETs and
Schottky diodes are selected. Finally, C
IN
and C
OUT
are
selected according to the voltage ripple requirements. The
circuit shown in Figure 1 can be configured for operation
up to a MOSFET supply voltage of 28V (limited by the
external MOSFETs and possibly the minimum on-time).
Operating Frequency
The IC uses a constant frequency, phase-lockable ar-
chitecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to the Phase-Locked
Loop and Frequency Synchronization section for additional
information.
A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 3. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 680kHz.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
PLLFLTR PIN VOLTAGE (V)
0
OPERATING FREQUENCY (kHz)
3731 F03
700
600
500
400
300
200
0.5 1 1.5 2 2.5
Figure 3. Operating Frequency vs V
PLLFLTR
LTC3731
14
3731fc
APPLICATIONS INFORMATION
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The PolyPhase approach reduces both input and output
ripple currents while optimizing individual output stages to
run at a lower fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current I
L
per individual section,
N, decreases with higher inductance or frequency and
increases with higher V
IN
or V
OUT
:
I
L
=
V
OUT
fL
1
V
OUT
V
IN
where f is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 4 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage
as the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against
the inductor ripple current at zero duty factor. The graph
can be used in place of tedious calculations. As shown in
Figure 4, the zero output ripple current is obtained when:
V
OUT
V
IN
=
k
N
where k = 1, 2,...,N 1
So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In appli-
cations having a highly varying input voltage, additional
phases will produce the best results.
Accepting larger values of I
L
allows the use of low in-
ductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
I
L
= 0.4(I
OUT
)/N, where N is the number of channels and
I
OUT
is the total load current. Remember, the maximum
I
L
occurs at the maximum input voltage. The individual
inductor ripple currents are constant, determined by the
input and output voltages and the inductance.
Inductor Core Selection
Once the value for L1 to L3 is determined, the type of induc-
tor must be selected. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores, forcing the use of ferrite, molypermalloy or
Kool Mµ cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase
in inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi-
cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3731 F04
6-PHASE
12-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
I
O(P-P)
V
O
/fL
Figure 4. Normalized Peak Output Current
vs Duty Factor [I
RMS
= 0.3(I
O(P-P)
]
LTC3731
15
3731fc
APPLICATIONS INFORMATION
Power MOSFET and D1, D2, D3 Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than one-third of the input voltage. In applications
where V
IN
>> V
OUT
, the top MOSFETs’ “on” resistance
is normally less important for overall efficiency than its
input capacitance at operating frequencies above 300kHz.
MOSFET manufacturers have designed special purpose
devices that provide reasonably low “on” resistance with
significantly reduced input capacitance for the main switch
application in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V
CC
, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”
resistance R
DS(ON)
, input capacitance, input voltage and
maximum output current.
MOSFET input capacitance is a combination of sev-
eral components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V
DS
voltage specified. C
MILLER
is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
RSS
and C
OS
are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =
V
IN
V
OUT
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN
=
V
OUT
V
IN
I
MAX
N
2
1+ δ
( )
R
DS(ON)
+
V
IN
2
I
MAX
2N
R
DR
( )
C
MILLER
( )
1
V
CC
V
TH(IL)
+
1
V
TH(IL)
f
( )
P
SYNC
=
V
IN
V
OUT
V
IN
I
MAX
N
2
1+ δ
( )
R
DS(ON)
+
V
DS
V
IN
3731 F05
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
Figure 5. Gate Charge Characteristic

LTC3731CG#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3-Phase Buck controller with PLL
Lifecycle:
New from this manufacturer.
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