LTC3731CG#PBF Datasheet LTC3731IG#PBF, LTC3731CG#TRPBF, LTC3731IG#TRPBF | P19-P21

LTC3731

3731fc

APPLICATIONS INFORMATION

The resistive divider is connected to the output as shown

in Figure 2, allowing remote voltage sensing.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) ON/OFF, 2)

soft-start and 3) a defeatable short-circuit latch off timer.

Soft-start reduces the input power sources’ surge cur-

rents by gradually increasing the controller’s current limit

(proportional to an internal buffered and clamped V

ITH

The latchoff timer prevents very short, extreme load tran-

sients from tripping the overcurrent latch. A small pull-up

current (>5µA) supplied to the RUN/SS pin will prevent

the overcurrent latch from operating. A maximum pull-

up current of 200µA is allowed into the RUN/SS pin even

though the voltage at the pin may exceed the absolute

maximum rating for the pin. This is a result of the limited

current and the internal protection circuit on the pin. The

following explanation describes how this function operates.

An internal 1.5µA current source charges up the C

ca-

pacitor. When the voltage on RUN/SS reaches 1.5V, the

controller is permitted to start operating. As the voltage on

RUN/SS increases from 1.5V to 3.5V, the internal current

limit is increased from 20mV/R

SENSE

to 75mV/R

SENSE

. The

output current limit ramps up slowly, taking an additional

1s/µF to reach full current. The output current thus ramps

up slowly, eliminating the starting surge current required

from the input power supply. If RUN/SS has been pulled

all the way to ground, there is a delay before starting of

approximately:

DELAY

1.5V

1.5µA

= 1s/µF

( )

IRAMP

3V − 1.5V

1.5µA

= 1s/µF

( )

By pulling the RUN/SS controller pin below 0.4V the IC is

put into low current shutdown (I

< 100 µA). The RUN/SS

pin can be driven directly from logic as shown in Figure 7.

Diode, D1, in Figure 7 reduces the start delay but allows

to ramp up slowly, providing the soft-start function.

The RUN/SS pin has an internal 6V zener clamp (see the

Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the

controllers when an overcurrent condition is detected. The

RUN/SS capacitor is used initially to turn on and limit the

inrush current of all three output stages. After the con-

trollers have been started and been given adequate time

to charge up the output capacitor and provide full load

current, the RUN/SS capacitor is used for a short-circuit

timer. If the output voltage falls to less than 70% of its

nominal value, the RUN/SS capacitor begins discharging

on the assumption that the output is in an overcurrent

condition. If the condition lasts for a long enough period,

as determined by the size of the RUN/SS capacitor, the

discharge current, and the circuit trip point, the controller

will be shut down until the RUN/SS pin voltage is recycled.

If the overload occurs during start-up, the time can be

approximated by:

LO1

>> (C

• 0.6V)/(1.5µA) = 4 • 10

)

If the overload occurs after start-up, the voltage on the

RUN/SS capacitor will continue charging and will provide

additional time before latching off:

LO2

>> (C

• 3V)/(1.5µA) = 2 • 10

)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the RUN/SS pin from V

as shown in Figure 7. When V

is 5V, a 200k resistance

will prevent the discharge of the RUN/SS capacitor

during an overcurrent condition but also shortens the

soft-start period, so a larger RUN/SS capacitor value

may be required.

Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem with

noise pick-up or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

RUN/SS PIN3.3V OR 5V

RUN/SS PIN

3731 F07

SHDNSHDN

Figure 7. RUN/SS Pin Interfacing

LTC3731

3731fc

APPLICATIONS INFORMATION

troubleshooting of the circuit and PC layout. The internal

foldback current limiting still remains active, thereby pro-

tecting the power supply system from failure. A decision

can be made after the design is complete whether to rely

solely on foldback current limiting or to enable the latchoff

feature by removing the pull-up resistor.

The value of the soft-start capacitor C

may need to be

scaled with output current, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

> (C

OUT

)(V

OUT

) (10

–4

) (R

SENSE

)

The minimum recommended soft-start capacitor of

= 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the

internal current foldback function. A negative impedance

is experienced when powering a switching regulator. That

is, the input current is higher at a lower V

and decreases

as V

is increased. Current foldback is designed to ac-

commodate a normal, resistive load having increasing

current draw with increasing voltage. The EAIN pin should

be artificially held 70% above its nominal operating level

of 0.6V, or 0.42V in order to prevent the IC from “folding

back” the peak current level. A suggested circuit is shown

in Figure 8.

The emitter of Q1 will hold up the EAIN pin to a voltage in

the absence of V

OUT

that will prevent the internal sensing

circuitry from reducing the peak output current. Remov-

ing the function in this manner eliminates the external

MOSFET’s protective feature under short-circuit conditions.

This technique will also prevent the short-circuit latchoff

function from turning off the part during a short-circuit

event and the peak output current will only be limited to

N • 75mV/R

SENSE

Undervoltage Reset

In the event that the input power source to the IC (V

)

drops below 4V, the RUN/SS capacitor will be discharged

to ground. When V

rises above 4V, the RUN/SS capacitor

will be allowed to recharge and initiate another soft-start

turn-on attempt. This may be useful in applications that

switch between two supplies that are not diode connected,

but note that this cannot make up for the resultant inter-

ruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This allows

the top MOSFET of output stage 1’s turn-on to be locked

to the rising edge of an external source. The frequency

range of the voltage controlled oscillator is ±50% around

the center frequency f

. A voltage applied to the PLLFLTR

pin of 1.2V corresponds to a frequency of approximately

400kHz. The nominal operating frequency range of the IC

is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type

that provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector will

not lock the internal oscillator to harmonics of the input

frequency. The PLL hold-in range, ∆f

, is equal to the

capture range, ∆f

∆

= ±0.5 f

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter components on the PLLFLTR pin. A simplified block

diagram is shown in Figure 9.

If the external frequency (f

PLLIN

) is greater than the os-

cillator frequency, f

OSC

, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency is

less than f

OSC

, current is sunk continuously, pulling down

the PLLFLTR pin. If the external and internal frequencies

are the same, but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

3731 F08

CALCULATE FOR

0.42V TO 0.55V

EAIN

LTC3731

Figure 8. Foldback Current Elimination

LTC3731

3731fc

APPLICATIONS INFORMATION

the phase difference. Thus, the voltage on the PLLFLTR pin

is adjusted until the phase and frequency of the external

and internal oscillators are identical. At this stable operat-

ing point, the phase comparator output is open and the

filter capacitor C

holds the voltage. The IC PLLIN pin

must be driven from a low impedance source such as a

logic gate located close to the pin. When using multiple

ICs for a phase-locked system, the PLLFLTR pin of the

master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A voltage of 1.7V or below applied to

the master oscillator’s PLLFLTR pin is recommended in

order to meet this requirement. The resultant operating

frequency will be approximately 550kHz for 1.7V.

The loop filter components (C

, R

) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C

and R

determine how fast the loop

acquires lock. Typically R

=10k and C

ranges from

0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration

that the IC is capable of turning on the top MOSFET. It is

determined by internal timing delays and the gate charge

of the top MOSFET. Low duty cycle applications may ap-

proach this minimum on-time limit and care should be

taken to ensure that:

ON MIN

( )

OUT

( )

If the duty cycle falls below what can be accommodated

by the minimum on-time, the IC will begin to skip every

other cycle, resulting in half-frequency operation. The

output voltage will continue to be regulated, but the ripple

current and ripple voltage will increase.

The minimum on-time for the IC is generally about 110ns.

However, as the peak sense voltage decreases the minimum

on-time gradually increases. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

If an application can operate close to the minimum on-time

limit, an inductor must be chosen that is low enough in

value to provide sufficient ripple amplitude to meet the

minimum on-time requirement. As a general rule, keep

the inductor ripple current for each channel equal to or

greater than 30% of I

OUT(MAX)

at V

IN(MAX)

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Checking Transient Response

The regulator loop response can be checked by look-

ing at the load transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

OUT

shifts by

an amount equal to

∆

LOAD

• ESR, where ESR is the ef-

fective series resistance of C

OUT

∆

LOAD

also begins to

charge or discharge C

OUT

, generating the feedback error

signal that forces the regulator to adapt to the current

change and return V

OUT

to its steady-state value. During

EXTERNAL

OSC

2.4V

10k

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PHASE

DETECTOR/

OSCILLATOR

PLLIN

3731 F09

PLLFLTR

50k

Figure 9. Phase-Locked Loop Block Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

LTC3731CG#PBF

Mfr. #:

Buy LTC3731CG#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators 3-Phase Buck controller with PLL

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LTC3731CG#PBF

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