Data Sheet AD8120
Rev. A | Page 9 of 16
THEORY OF OPERATION
The AD8120 is a triple, digitally controlled analog delay line,
optimized for correcting delay skew between individual channels
in common wired communication media such as unshielded
twisted pair (UTP), shielded twisted pair (STP), and coaxial
cables. In these applications, the AD8120 is used to time-align
three video signals, usually RGB or YPbPr, that arrive at a
receiver at different times due to variations in total delay per
channel. Although its primary application is analog video, the
AD8120 can be applied in other systems that require variable
analog delays up to 50 ns with 0.8 ns resolution.
The three channels consist of cascaded delay sections that are
switched in such a way as to provide a total of 50 ns total delay
difference between channels with 0.8 ns resolution. A fixed
propagation delay is common to all channels, where the associated
delay is set to 0. Therefore, the delay setting for a given channel is
a measure of the relative delay among the channels, rather than
an absolute delay.
There are three options for controlling the delay: serial periph-
eral interface (SPI) serial bus, I
2
C serial bus, and analog control
voltage. Two pins select the type of control: the MODE pin selects
analog or digital control, and the SER_SEL pin selects the SPI or
I
2
C serial bus (see Table 5).
Table 5. Modes of Control
PD
(Pin 5)
MODE (Pin 7) SER_SEL (Pin 6) Control Type
0 X X Power-down
1 0 0 I
2
C control
1 0 1 SPI control
1 1 X Analog control
In analog control mode, three control voltages, V
CR
, V
CG
, and
V
CB
, control the delay of each channel. These voltages are
converted internally to digital codes with 0.8 ns steps.
Each AD8120 channel has a fixed overall gain of 2 and can
drive up to four double-terminated 75 Ω cables or PCB traces.
A power-down feature can shut down the AD8120 for power
saving when not in use.
CONTROLLING THE DELAY
The delay time of each of the three channels is controlled in one
of three ways. One control option is the application of analog
control voltages to the V
CR
, V
CG
, and V
CB
inputs. The other two
control options are via the SPI or I
2
C serial digital bus. The delay
is set in discrete amounts with a nominal resolution of 0.8 ns per
quantization level (or LSB), even in the analog control mode.
A delay code is assigned to each quantization level, ranging from
0 to 63 in decimal format. The means of control (analog, SPI, or
I
2
C) is selected by applying the appropriate logic levels to the
MODE and SER_SEL inputs (see Table 5). All three channels
must use the same delay control option in a given application.
It is important to note that in skew correction applications, the
metric is the relative delay between channels, not the absolute
delay. Each channel of the AD8120 exhibits a constant delay at
its zero delay setting, referred to as its propagation delay. This
propagation delay is well matched between the channels and is
subtracted out when performing skew correction. The delay
codes, therefore, ignore the constant propagation delay and
refer only to adjustable delay beyond the propagation delay.
Delay can be calculated by multiplying the delay code by 0.8 ns.
For example, setting the red delay to 8 ns (delay code = 10), the
green delay to 16 ns (delay code = 20), and the blue delay to 28 ns
(delay code = 35) produces the following relative delays: green
delayed by 8 ns relative to red, blue delayed by 20 ns relative to
red, and blue delayed by 12 ns relative to green. If an application
requires control of absolute delay, the propagation delay must be
added to the delay corresponding to the associated delay code.
SETTING THE DELAY
In most video skew compensation applications, it is best to set
the delay of the path with the longest delay to 0, and then to add
delay to the other paths to match the longest delay. In this way,
the bandwidth of each path is maximized, and the noise of each
path is minimized. Figure 16 illustrates a case where a test step
is applied simultaneously to each cable input, and the green
cable delay is the longest.
RED CABLE OUTPUT
28ns
GREEN CABLE OUTPUT
BLUE CABLE OUTPUT
40ns
07838-022
Figure 16. Cable Delay Example
In the example in Figure 16, the AD8120 green delay should be
set to 0. The AD8120 red delay is then set to the delay difference
between the green and red outputs, or 40 ns. Finally, the AD8120
blue delay is set to the delay difference between the green and blue
outputs, or 28 ns. Using the digital delay codes, green delay = 0,
red delay = 50, and blue delay = 35.
AD8120 Data Sheet
Rev. A | Page 10 of 16
ANALOG CONTROL
A number of video transmission systems do not have a microcon-
troller embedded or otherwise available to provide digital control.
These systems require analog control. Potentiometer control is
one of the most common ways to implement analog control (see
Figure 25). To select analog control, set the MODE pin high.
The AD8120 has one analog control input for each channel: V
CR
,
V
CG
, and V
CB
. The maximum recommended control voltage range
on these inputs is 0 V to 2.0 V, although the actual control range
where delay changes take effect is smaller and lies within this larger
range. An internal ADC converts the analog control voltages
into binary delay codes; therefore, the analog control is discrete
with nominally 0.8 ns resolution. Figure 6 illustrates the typical
transfer characteristic between control voltage and delay code.
POWER DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. Note that
the input high level for the power-down input is higher than it
is for the other digital inputs. Refer to the Specifications in
Table 1 for details.
DIGITAL CONTROL
Set the MODE pin low to select digital control (SPI or I
2
C). Set
the SER_SEL pin high to select SPI mode, or set the SER_SEL
pin low to select I
2
C mode. Table 6 provides the bit values for
reading and writing the red, green, and blue registers.
Table 6. Read/Write Instruction and Color Registers
Operation
R/
W
Bit
C1 Bit C0 Bit
Write Red 0 0 0
Read Red 1 0 0
Write Green 0 0 1
Read Green 1 0 1
Write Blue
0
1
0
Read Blue 1 1 0
SPI Control
The SPI bus operates in full-duplex mode and consists of four
digital lines: SDI, SDO, SCK, and
CS
.
Table 7. AD8120 SPI Pin Descriptions
Pin No.
Pin
Name Description
29 SDI Serial data input, master out slave in (MOSI)
2 SDO Serial data output, master in slave out (MISO)
30 SCK Serial clock from master
31
CS
Chip select; active low
The AD8120 is programmed in SPI mode using a 2-byte sequence
(see Table 8). Data is clocked into the SDI pin or clocked out of
the SDO pin on the rising edge of the clock, MSB first. The first
byte contains the read/write (R/
W
) instruction and the color reg-
ister address (see Table 6). The second byte contains the delay
code to write to the part (R/
W
= 0) or the stored delay code to
read from the part (R/
W
= 1).
Figure 17 shows how to write Delay Code 42 to the green
register. Figure 18 shows how to read Delay Code 21 from
the blue register.
Table 8. SPI 2-Byte Sequence
Byte 1 (R/
W
Bit and Color Register) Byte 2 (Data)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SDI R/
W
0 0 0 0 0 C1 C0 X X D5 D4 D3 D2 D1 D0
SDO X X X X X X X X X X D5 D4 D3 D2 D1 D0
Data Sheet AD8120
Rev. A | Page 11 of 16
BYTE 2
DATA
BYTE 1
R/W BIT AND COLOR REGISTER
START
STOP
CS
SCK
SDI
SDO
0 0 0 0 0 0 0 1
X X X X X X X X
X X 1 0 1 0 01
XX X X X X X X
07839-025
Figure 17. Setting the Green Register to Delay Code 42 Using SPI
BYTE 2
DATA
BYTE 1
R/W BIT AND COLOR REGISTER
START
STOP
CS
SCK
SDI
SDO
1 0 0 0 0 0 1 0
X X 0 1 0 1 0 1
X X X X X X XX
XX X X X X X X
07839-026
Figure 18. Reading Delay Code 21 from the Blue Register Using SPI

AD8120ACPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs Trple Skew-Compenst Video Delay Line
Lifecycle:
New from this manufacturer.
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