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AD8120ACPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD8120 Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD ON UNDERSIDE OF DEVICE
MUST BE CONNECTED TO PCB PLANE.
07839-003
24 GND
23
V
CR
22
V
CG
21
V
CB
20
V
REF
19 DNC
18 GND
17
V
S+
1
2
3
4
5
6
7
8
GND
SDO/SDA
DNC
DNC
PD
SER_SEL
MODE
GND
9
10
11
12
13
14
15
16
V
S–
GND
B
OUT
GND
G
OUT
GND
R
OUT
V
S+
32
31
30
29
28
27
26
25
GND
CS/A0
SCK/SCL
SDI/A1
B
IN
G
IN
R
IN
V
S+
R
d
G
d
B
d
DIGITAL
CONTROL
ANALOG
CONTROL
AD8120
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 10, 12, 14,
18, 24, 32
GND
Ground.
2 SDO/SDA Serial Data Output for SPI Bus/Bidirectional Serial Data Line for I
2
C Bus.
3, 4, 19 DNC Do Not Connect.
5
PD
Power-Down.
6 SER_SEL Selection of SPI Serial Bus or I
2
C Serial Bus (I
2
C = 0, SPI = 1).
7 MODE Selection of Analog Control Mode or Digital Control Mode (Digital = 0, Analog = 1).
9 V
S−
Negative Power Supply. Connect to −5 V.
11 B
OUT
Blue Channel Video Output.
13 G
OUT
Green Channel Video Output.
15 R
OUT
Red Channel Video Output.
16, 17, 25 V
S+
Positive Power Supply. Connect to +5 V.
20 V
REF
Internal Reference Bypass. Connect a 0.01 μF capacitor between this pin and GND.
21 V
CB
Analog Delay Control Voltage, Blue Channel.
22 V
CG
Analog Delay Control Voltage, Green Channel.
23 V
CR
Analog Delay Control Voltage, Red Channel.
26 R
IN
Red Channel Video Input.
27
G
IN
Green Channel Video Input.
28 B
IN
Blue Channel Video Input.
29 SDI/A1 Serial Data Input for SPI Bus/I
2
C Address Bit 1.
30 SCK/SCL Serial Clock for SPI Bus/Serial Clock for I
2
C Bus.
31
CS
/A0 Chip Select for SPI Bus/I
2
C Address Bit 0.
Exposed Pad EP Thermal Plane Connection. Connect the exposed pad on the underside of the AD8120 to any PCB
plane with voltage between V
S+
and V
S−
.
Data Sheet AD8120
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, V
S
= ±5 V, R
L
= 150 Ω, 10% to 90% input rise/fall time (t
R
/t
F
) = 4 ns, unless otherwise noted.
4
2
0
–2
–4
–6
–8
–10
–12
0.3 1 10 100 1k
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
07839-010
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 1
DELAY CODE = 2
Figure 4. Small-Signal Frequency Response for Various Delay Settings,
V
OUT
= 0.2 V p-p
0.25
0.20
0.15
0.10
0.05
0
–0.05
–20 0 20 40 60 80 100 120
TIME (ns)
AMPLITUDE (V)
07839-012
DELAY CODE = 63
DELAY
CODE = 33
DELAY CODE = 0
INPUT
V
S
= ±5V
LOAD = 150Ω
Figure 5. Small-Signal Pulse Response for Various Delay Settings
50
45
40
35
30
25
20
15
10
5
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1 12 22 33 44 55 62
ANALOG CONTROL VOLTAGE (V)
DELAY CODE
RELATIVE DELAY (ns)
07839-021
Figure 6. Relative Delay vs. Delay Code and Analog Control Voltage
4
6
2
0
–2
–4
–6
–8
–10
–12
0.3 1 10 100 1k
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
07839-011
DELAY CODE = 63
DELAY CODE = 33
DELAY CODE = 1
DELAY CODE = 2
Figure 7. Video Signal Frequency Response for Various Delay Settings,
V
OUT
= 1.4 V p-p
1.8
0.8
1.0
1.2
1.4
1.6
0.6
0.4
0.2
0
–0.2
–20 0 20 40 60 80 100 120
TIME (ns)
AMPLITUDE (V)
07839-013
DELAY CODE = 63
DELAY CODE = 33
V
S
= ±5V, LOAD = 150Ω
DELAY CODE = 0
INPUT
Figure 8. Large-Signal Pulse Response for Various Delay Settings
120
110
100
90
80
70
60
50
40
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DELAY CODE
QUIESCENT CURRENT (mA)
07839-018
TWO CHANNELS
ONE CHANNEL
THREE CHANNELS
Figure 9. Quiescent Current vs. Delay Code
AD8120 Data Sheet
Rev. A | Page 8 of 16
0
–30
–20
–10
–50
–40
–60
–70
–80
–90
–100
0.3 1 10 100 1k
FREQUENCY (MHz)
OUTPUT LEVEL (dB)
07839-014
DELAY CODE = 63
DELAY CODE = 0
DRIVING R AND B SIMULTANEOUSLY
MEASURING G
Figure 10. Crosstalk on Green Channel vs. Frequency,
V
OUT
= 1.4 V p-p
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
OUTPUT VOLTAGE NOISE DENSITY (nV/ Hz)
07839-016
10k
1k
100
10
DELAY CODE = 63
DELAY CODE = 0
Figure 11. Output Voltage Noise Density vs. Frequency
5
4
3
2
1
0
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DELAY CODE
RISE/FALL TIME (ns)
07839-019
TYPICAL RISE TIME
TYPICAL FALL TIME
Figure 12. 10% to 90% Rise/Fall Time vs. Delay Code,
V
OUT
= 1.4 V p-p, V
IN
Rise/Fall = 2 ns
20
10
0
–10
–20
–30
–40
–50
0.3 1 10 100 1k
FREQUENCY (MHz)
POWER SUPPLY REJECTION RATIO (dB)
07839-015
V
S+
PSRR AT DELAY CODE 0
V
S+
PSRR AT DELAY CODE 63
V
S–
PSRR AT DELAY CODE 0
V
S–
PSRR AT DELA
Y CODE 63
Figure 13. PSRR vs. Frequency
5
4
3
2
1
0
0
DELAY CODE
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
INTEGRATED OUTPUT VOLTAGE NOISE (mV rms)
07839-017
Figure 14. Integrated Output Voltage Noise vs. Delay Code,
100 kHz to 160 MHz
160
140
120
100
80
60
40
20
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
QUIESCENT CURRENT (mA)
07839-020
V
S+
, RGB DELAY CODE 63
V
S+
, RGB DELAY CODE 0
V
S+
, DISABLED
V
S+
, RG DELAY CODE 63, B DELAY CODE 0
V
S+
, R DELAY CODE 63, GB DELAY CODE 0
Figure 15. Quiescent Current vs. Temperature
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD8120ACPZ-RL

Mfr. #:
Buy AD8120ACPZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs Trple Skew-Compenst Video Delay Line
Lifecycle:
New from this manufacturer.
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