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AD8120ACPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Data Sheet AD8120
Rev. A | Page 3 of 16
SPECIFICATIONS
T
A
= 25°C, V
S
= ±5 V, R
L
= 150 Ω, 10% to 90% input rise/fall time (t
R
/t
F
) = 4 ns, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DELAY CHARACTERISTICS
Total Adjustable Delay Range Delay Code 63 to Delay Code 0 50 ns
Delay Resolution Monotonic, 1 LSB 0.8 ns
Propagation Delay Delay = 0 ns 4.9 ns
Channel-to-Channel Delay Error All channels at maximum delay 0.4 ns
DYNAMIC PERFORMANCE
−3 dB Video Signal Bandwidth V
OUT
= 1.4 V p-p, delay = 0 ns 200 MHz
V
OUT
= 1.4 V p-p, delay = 50 ns 150 MHz
−3 dB Small-Signal Bandwidth V
OUT
= 0.2 V p-p, delay = 0 ns 165 MHz
OUT
140
MHz
0.1 dB Video Signal Flatness V
OUT
= 1.4 V p-p, delay = 0 ns 27 MHz
V
OUT
= 1.4 V p-p, delay = 50 ns 35 MHz
10% to 90% Rise/Fall Time V
OUT
= 1.4 V step, delay = 0 ns 2.5/3 ns
V
OUT
= 1.4 V step, delay = 50 ns 3/4.2 ns
Settling Time to 1% V
OUT
= 1.4 V step, delay = 0 ns 8 ns
V
OUT
= 1.4 V step, delay = 50 ns 18 ns
Slew Rate V
OUT
= 1.4 V step, delay = 0 ns, rising edge 550 V/μs
V
OUT
= 1.4 V step, delay = 0 ns, falling edge 540 V/μs
V
OUT
= 1.4 V step, delay = 50 ns, rising edge 510 V/μs
V
OUT
= 1.4 V step, delay = 50 ns, falling edge 360 V/μs
Overshoot V
OUT
= 1.4 V step, delay = 0 ns 1 %
V
OUT
= 1.4 V step, delay = 50 ns 20 %
Gain 0 ns to 50 ns delay 1.95 2.01 2.06 V/V
Channel-to-Channel Gain Matching Over all codes, among all channels 0.8 3 %
Hostile Crosstalk Measured on G with R and B driven at 1 MHz,
V
OUT
= 1.4 V p-p, delay = 0 ns
−80 dB
VIDEO INPUT CHARACTERISTICS R
IN
, G
IN
, B
IN
Input Bias Current 0.8 1.5 μA
Input Capacitance 1 pF
Input Resistance 500 kΩ
VIDEO OUTPUT CHARACTERISTICS R
OUT
, G
OUT
, B
OUT
Output Voltage Swing
±3.25
V
Output Current 50 mA
Integrated Output Noise 100 kHz to 160 MHz
Delay = 0 ns 1 mV rms
Delay = 50 ns 4 mV rms
Output Offset Voltage (RTI)
−30
0
+30
mV
Channel-to-Channel Output Offset Voltage
Matching (RTI)
Over all codes, among all channels 30 mV
Output Impedance
PD
high, at 20 MHz 1.5 Ω
ANALOG CONTROL INPUT CHARACTERISTICS
Input Bias Current V
CR
, V
CG
, V
CB
1 μA
Operating Range V
CR
, V
CG
, V
CB
0 2 V
Delay Voltage Step Size in Linear Range ΔV
CR
, ΔV
CG
, ΔV
CB
to move one delay LSB 28 mV
AD8120 Data Sheet
Rev. A | Page 4 of 16
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL CONTROL INPUT CHARACTERISTICS
(SEE BELOW FOR POWER DOWN)
SDO/SDA, SCK/SCL, SDI/A1,
CS
/A0, SER_SEL,
MODE
Input Bias Current 2 μA
Input High Voltage 2.6 V
Input Low Voltage
0.6
V
Output High Voltage 4.5 V
Output Low Voltage 0.6 V
POWER DOWN CHARACTERISTICS
PD
Input High Voltage 4.0 V
Input Low Voltage 0.6 V
SPI TIMING CHARACTERISTICS
Clock Frequency SCK 10 MHz
CS
Setup Time, t
1
CS
to SCK 5 ns
Clock Pulse High, t
2
SCK 50 ns
Clock Pulse Low, t
3
SCK 50 ns
Data Setup Time, t
4
SDI to SCK 5 ns
Data Hold Time, t
5
SDI to SCK 5 ns
CS
Hold Time, t
6
SCK to
CS
5 ns
I
2
C TIMING CHARACTERISTICS
Clock Frequency SCL 100 kHz
Start Setup Time, t
1
SDA to SCL 10 ns
Clock Pulse High, t
2
SCL 5 μs
Clock Pulse Low, t
3
SCL 5 μs
Data Setup Time, t
4
SDA (input) to SCL 100 ns
Data Hold Time, t
5
SDA (input) to SCL 100 ns
Hold Time, t
6
SCL to SDA 10 ns
POWER SUPPLY
Positive Supply Range 4.5 5.5 V
Negative Supply Range −5.5 −4.5 V
Positive Quiescent Current Delay = 0 ns 44 mA
Delay = 50 ns 114 mA
Powered down,
PD
low 4 mA
Negative Quiescent Current Delay = 0 ns 37 mA
Delay = 50 ns 108 mA
Powered down,
PD
low 0.5 mA
Quiescent Current Drift T
MIN
to T
MAX
, delay = 0 ns 0.13 mA/°C
T
MIN
to T
MAX
, delay = 50 ns 0.36 mA/°C
+PSRR R
L
= 150 Ω, delay = 50 ns 56 dB
−PSRR R
L
= 150 Ω, delay = 50 ns 44 dB
Data Sheet AD8120
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±6 V
Internal Power Dissipation
32-Lead LFCSP at T
A
= 25°C 3.5 W
Input Voltage V
S−
− 0.3 V to V
S+
+ 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering 10 sec)
300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, for a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
5 mm × 5 mm, 32-Lead LFCSP 36 2 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8120 package is
limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by
the glass transition temperature of the plastic, is approximately
150°C. Temporarily exceeding this limit may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (V
S+
and V
S−
) times the quiescent current (I
S
). Power dissipated due
to load drive depends upon the particular application. It is cal-
culated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
Airflow increases heat dissipation by reducing θ
JA
.
To ensure optimal thermal performance, the exposed paddle
must be in an optimized thermal connection with an external
plane layer.
6
5
4
3
2
1
0
–40 –20 0 20 40 60 80
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
07839-002
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
on a JEDEC Standard 4-Layer Board
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD8120ACPZ-RL

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Buy AD8120ACPZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs Trple Skew-Compenst Video Delay Line
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