THine Electronics, Inc.
Security E
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
Switching Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
tDEH
DE=High Duration 2tTCIP - - sec
tDEL DE=Low Duration 2tTCIP - - sec
Table 15. DE requirement
Symbol Parameter Conditions Min. Typ. Max. Units
COL[1:0]=L,L | L,H 10 - 50 ns
COL[1:0]=H,L 11.76 - 50 ns
COL[1:0]=H,H 13.3 - 50 ns
tTCIH LVDS Differential Clock High Time 2×tTCIP/7 - 5×tTCIP/7 ns
tTCIL LVDS Differential Clock Low Time 2×tTCIP/7 - 5×tTCIP/7 ns
tTCIP=75MHz -440 - 440 ps
tTCIP=85MHz -390 - 390 ps
tTCIP=100MHz -330 - 330 ps
tTIP1 LVDS Input Data Position0 -tSK 0 +tSK ns
tTIP0 LVDS Input Data Position1 tTCIP/7-tSK tTCIP/7 tTCIP/7+tSK ns
tTIP6 LVDS Input Data Position2 2×tTCIP/7-tSK 2×tTCIP/7 2×tTCIP/7+tSK ns
tTIP5 LVDS Input Data Position3 3×tTCIP/7-tSK 3×tTCIP/7 3×tTCIP/7+tSK ns
tTIP4 LVDS Input Data Position4 4×tTCIP/7-tSK 4×tTCIP/7 4×tTCIP/7+tSK ns
tTIP3 LVDS Input Data Position5 5×tTCIP/7-tSK 5×tTCIP/7 5×tTCIP/7+tSK ns
tTIP2 LVDS Input Data Position6 6×tTCIP/7-tSK 6×tTCIP/7 6×tTCIP/7+tSK ns
tTISK Lane0/1 LVDS Input Clock Skew -0.3×tTCIP - 0.3×tTCIP ns
tTRF CML Output Rise and Fall Time(20%-80%) 50 - 150 ps
tTOSK CML Lane0/1 Output Inter Pair Skew -2 - 2 UI
tTCD Input Clock to Output Data Delay
(56/(5×n)+6.1)
×tTCIP-5 (1)
(56/(5×n)+6.1)
×tTCIP+5 (1)
tTPD Power On to PDN High Delay 0 - - ns
tTPLL0 PDN High to CML Output Delay - - 10 ms
tTPLL1 PDN Low to CML Output High Fix Delay - - 20 ns
LOCKN High to Training Pattern Output
Delay
LOCKN Low to Data Pattern Output
Delay
(1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively.
LVDS Receiver Skew Margin
Table 16. THCV215 Switching Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
COL[1:0]=L,L | L,H 333 tTCIP/30 1667 ps
COL[1:0]=H,L 294 tTCIP/40 1250 ps
COL[1:0]=H,H 266 tTCIP/50 1000 ps
tRISK CML Lane0/1 Input Inter Pair Skew Margin - - 15 UI
tRLVT LVDS Differential Output Transition Time - 0.6 1.5 ns
tROP1 LVDS Output Data Position0 -0.25 0 0.25 ns
tROP0 LVDS Output Data Position1 tTCIP/7-0.25 tTCIP/7 tTCIP/7+0.25 ns
tROP6 LVDS Output Data Position2 2×tTCIP/7-0.25 2×tTCIP/7
tROP5 LVDS Output Data Position3 3×tTCIP/7-0.25 3×tTCIP/7
tROP4 LVDS Output Data Position4 4×tTCIP/7-0.25 4×tTCIP/7
tROP3 LVDS Output Data Position5 5×tTCIP/7-0.25 5×tTCIP/7
tROP2 LVDS Output Data Position6 6×tTCIP/7-0.25 6×tTCIP/7
tROSK Lane0/1 LVDS Output Clock Skew - - 50 ps
tRDC Input Data to Output Clock Delay
tRPD Power On to PDN High Delay 0 - - ns
tRHPD0 PDN High to HTPDN Low Delay - - 1 us
tRHPD1 PDN Low to HTPDN High Delay - - 1 us
Training Pattern Input to LOCKN Low
Delay
tRPLL1 PDN Low to LOCKN High Delay - - 10 us
tRLCK0 LOCKN Low to LVDS Output Delay - - 1 ms
tRLCK1 LOCKN High to LVDS High-Z Delay - - 0 ns
(1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively.
Table 17. THCV216 Switching Characteristics
