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THCV215

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
THine Electronics, Inc.
Security E
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
Pin Description
THCV215 THCV216
Pin Name Pin # Type* Description Pin Name Pin # Type* Description
TX0 +/- 50,51 CO RX0 +/- 15,14 CI
TX1 +/- 47,48 CO RX1 +/- 19,18 CI
TLA0+/- 4,3 LI RLA0+/- 61,62 LO
TLB0+/- 6,5 LI RLB0+/- 59,60 LO
TLC0+/- 8,7 LI RLC0+/- 57,58 LO
TLCLK0+/- 10,9 LI RLCLK0+/ 55,56 LO
TLD0+/- 12,11 LI RLD0+/- 53,54 LO
TLE0+/- 14,13 LI RLE0+/- 51,52 LO
TLF0+/- 16,15 LI RLF0+/- 49,50 LO
TLA1+/- 18,17 LI RLA1+/- 47,48 LO
TLB1+/- 20,19 LI RLB1+/- 45,46 LO
TLC1+/- 22,21 LI RLC1+/- 43,44 LO
TLCLK1+/- 24,23 LI RLCLK1+/ 41,42 LO
TLD1+/- 26,25 LI RLD1+/- 39,40 LO
TLE1+/- 28,27 LI RLE1+/- 37,38 LO
TLF1+/- 30,29 LI RLF1+/- 35,36 LO
LOCKN 56 I Lock detect input LOCKN 7 O Lock detect output (open drain)
HTPDN 57 I Hot plug detect input HTPDN 6 O Hot plug detect output (open drain)
PDN 58 I
Power down input
H: Normal Operation
L: Power down (CML output High Fix,
other High-Z)
PDN 27 I
Power down input
H: Normal Operation
L: Power down (High-Z)
COL1,
COL0
61,60 I
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
H,H: 12bit
COL1,
COL0
4,5 I
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
H,H: 12bit
SDSEL 62 I
Single/Dual select input
L: Channel0 enable, Channel1 disable
H: Channel0, Channel1 enable
SDSEL 3 I
Single/Dual select input
L: Channel0 enable, Channel1 disable
H: Channel0, Channel1 enable
DRV1 42 I Must be tied to GND
DRV0 41 I Must be tied to VDL
PRE1,
PRE0
40,39 I
Pre-emphasis level select input
L,L: 0%
H,L: 100%
L,H: not available
H,H: not available
RDY 59 O
Link status ready output
L: not ready
H: ready
Reserved
1,2
26,28 I Must be tied to GND
Reserved1 37 I
Field BET mode enable input
L: Normal operation (default)
H: Field BET mode enabled
Reserved3 29 I
Field BET mode enable input
L: Normal operation (default)
H: Field BET mode enabled
Reserved0 38 I Must be tied to GND VDL 8,25 P 1.8V power supply pin for digital circuitry
GND 9,24 P Ground pin for digital circuitry
CAVDL 12,21 P 1.8V power supply pin for CML input
GND 36,54 P Ground pin for digital circuitry CAGND
13,16,
17,20
P Ground pin for CML input
CAVDL 45,53 P 1.8V power supply pin for CML output CPVDL0 10 P 1.8V power supply pin for PLL circuitry
CAGND 46,49,52 P Ground pin for CML output CPGND0 11 P Ground pin for PLL circuitry
CPVDL 43 P 1.8V power supply pin for PLL circuitry CPVDL1 23 P 1.8V power supply pin for PLL circuitry
CPGND 44 P Ground pin for PLL circuitry CPGND1 22 P Ground pin for PLL circuitry
LPVDL 33,64 P
1.8V power supply pin for LVDS PLL
LPVDH 1,32 P
3.3V power supply pin for LVDS PLL
LPGND 34,63 P Ground pin for LVDS PLL circuitry LPGND 2,31 P Ground pin for LVDS PLL circuitry
LAVDH 2,31 P 3.3V power supply pin for LVDS input LAVDH 34,63 P 3.3V power supply pin for LVDS output
LAGND 1,32 P Ground pin for LVDS input LAGND 33,64 P Ground pin for LVDS output
*type symbol
Note) All CMOS inputs are 1.8V-inputs I=1.8V CMOS Input, O=1.8V CMOS Output, IO3=3.3V CMOS I/O
except for THCV216's RS LI=LVDS Input, LO= LVDS Output
CI=CML Input, CO=CML Output
P=Power
VDL
35,55
P
1.8V power supply pin for digital circuitry
RS
30
IO3
Direction of RS pin depends on
Reserved3.
LVDS swing range select input
when Reserved3=L
H: Normal swing (350mV typ.)
L: Reduced swing (200mV typ.)
Field BET output when Reserved3=H.
Goes LOW when errors detected.
CML Data Input
LVDS Data Output
LVDS Data Input
CML Data Output
4/26
THine Electronics, Inc.
Security E
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
Functional Description
Functional Overview
With V-by-One
®
HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV215
and THCV216 enable transmission of 18/24/30/36bits per pixel video data (Rn/Gn/Bn/CONTn), Hsync
(HSYNCn), Vsync (VSYNCn) data and Data Enable (DE) by single/dual differential pair cable with minimal
external components.
THCV215, the transmitter, inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video
data and Hsync, Vsync data separately, depending on the polarity of DE. DE is a signal which indicates whether
video or Hsync, Vsync data are active. When DE is high, it serializes video data inputs into a single differential
data stream. And it transmits serialized Hsync, Vsync data when DE is low.
THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial
data into video data with DE being high or Hsync, Vsync data with DE being low, recognizing which type of
serial data is being sent by the transmitter. And it outputs the recovered data in the form of LVDS data.
THCV216 can seamlessly operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps/channel,
detecting the frequency of an incoming data stream, and recovering both the clock and data by itself.
It does not need any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE as described in Figure 2, Figure 3 and Table 15.
Dual LVDS input to THCV215 should be synchronized in terms of DE transition. See Figure 2.
If DE=Low, Hsync and Vsync data of same cycle are transmitted. Otherwise video data of that are transmitted
(DE=High). SYNC data from receiver in DE=High period are previous data of DE transition. See Figure 3.
The length of DE being low and high is at least 2 clock cycles long as described in Table 15.
Data Enable must be toggled like High -> Low -> High at regular interval.
Figure 1. Conceptual diagram of the basic operation of the chipset
Figure 2. Service condition of DE input synchronization
Vdiff = (TLCLK0+) – (TLCLK0-)
Vdiff = (TLCLK1+) – (TLCLK1-)
Vdiff = (TLC0+) – (TLC0-)
Vdiff = (TLC1+) – (TLC1-)
DE DE DE DE DE DE
DE DE DE DE DE DE
H
L
DE
THCV
216
THCV
215
DE
D[39:0]
Hsync
Vsync
Rn/Gn/Bn
CONTn
HSYNCn
VSYNCn
H
L
D[39:0]
Hsync
Vsync
Rn/Gn/Bn
CONTn
HSYNCn
VSYNCn
5/26
THine Electronics, Inc.
Security E
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
DE
VSYNCn
HSYNCn
Rn/Gn/Bn
CONTn
tDEH tDEL
1 cycle
Valid Data Valid Data
Low LowValid Data
Low High
Keep the last data
of DE=L period
THCV216
Output
Low
DE
VSYNC
HSYNC
Rn/Gn/Bn
CONTn
tDEH tDEL
1 cycle
Valid Data Valid Data
Invalid InvalidValid Data
Low High
Invalid
THCV215
Input
Low
n=0,1
n=0,1
Figure 3. Video and sync data transmission timing diagram
Single/Dual Link mode function (SDSEL)
SDSEL
Mode
Function
H
Single
Channel 0 active and channel 1 power down
L
Dual
Both channel 0 and channel 1 active
Table 1. Single/Dual mode select
Color Depth mode function (COL [1:0])
COL[1:0]
Color Depth
LVDS Clock Frequency Range
L,L
6bit
20MHz to 100MHz
L,H
8bit
20MHz to 100MHz
H,L
10bit
20MHz to 85MHz
H,H
12bit
20MHz to 75MHz
Table 2. Color depth mode select
6/26
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

THCV215

Mfr. #:
Buy THCV215
Manufacturer:
CEL
Description:
High-speed Video Data Transmitter and Receive
Lifecycle:
New from this manufacturer.
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