AD7151
Rev. 0 | Page 9 of 28
2
–2
–1
0
1
–50 1007550250–25
EXC FREQUENCY ERROR (%)
TEMPERATURE (°C)
07086-116
Figure 16. EXC Frequency Error vs. Temperature,
V
DD
= 3.3 V
2
–2
–1
0
1
2.7 3.63.33.0
EXC FREQUENCY ERROR (%)
V
DD
(V)
07086-117
Figure 17. EXC Frequency Error vs. V
DD
0
–80
–60
–40
–20
022.01.51.00.5
GAIN (dB)
INPUT SIGNAL FREQUENCY (kHz)
.5
07086-118
Figure 18. Capacitance to Digital Converter Frequency Response
0.50
–0.50
–0.25
0
0.25
06483216
CAPDAC DNL (LSB)
CAPDAC CODE
4
07086-119
Figure 19. CAPDAC Differential Nonlinearity (DNL),
V
DD
= 3.3 V
AD7151
Rev. 0 | Page 10 of 28
ARCHITECTURE AND MAIN FEATURES
DIGITAL
FILTER
POWER-DOWN
TIMER
CLOCK
GENERATOR
SERIAL
INTERFACE
POWER SUPPLY
MONITOR
CIN
C
X
EXC
Σ-Δ CDC
EXCITATION
CAPDAC
THRESHOLD
SCL
VDD
GND
AD7151
SDA
PROGRAMMING
INTERFACE
DIGITAL
OUTPUT
OUT
3.3
V
07086-010
Figure 20. AD7151 Block Diagram
The AD7151 core is a high performance capacitance-to-digital
converter (CDC) that allows the part to be interfaced directly to
a capacitive sensor.
The comparator compares the CDC result with thresholds, either
fixed or dynamically adjusted by the on-chip adaptive threshold
algorithm engine. Thus, the output indicates a defined change in
the input sensor capacitance.
The AD7151 also integrates an excitation source and CAPDAC
for the capacitive inputs, an input multiplexer, a complete clock
generator, a power-down timer, a power supply monitor, control
logic, and an I
2
C®-compatible serial interface for configuring the
part and accessing the internal CDC data and status, if required
in the system (see
Figure 20).
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 21 shows the CDC simplified functional diagram. The
converter consists of a second-order sigma delta (Σ-Δ), charge
balancing modulator and a third-order digital filter. The
measured capacitance C
X
is connected between an excitation
source and the Σ-Δ modulator input. The excitation signal is
applied on the C
X
during the conversion, and the modulator
continuously samples the charge going through the C
X
. The
digital filter processes the modulator output, which is a stream
of 0s and 1s containing the information in 0 and 1 density. The
data is processed by the adaptive threshold engine and output
comparators; the data can be also read through the serial interface.
The AD7151 is designed for floating capacitive sensors.
Therefore, both C
X
plates have to be isolated from ground or
any other fixed potential node in the system.
The AD7151 features slew rate limiting on the excitation voltage
output, which decreases the energy of higher harmonics on the
excitation signal and dramatically improves the system
electromagnetic compatibility (EMC).
DIGITAL
FILTER
0x000 TO 0xFFF
DATA
CLOCK
GENERATOR
CAPACITANCE TO DIGITAL CONVERTER
(CDC)
CIN
C
X
0pF TO 4pF
EXC
EXCITATION
Σ-Δ
MODULATOR
07086-011
Figure 21. CDC Simplified Block Diagram
CAPDAC
The AD7151 CDC core maximum full-scale input range is 4 pF.
However, the part can accept a higher capacitance on the input,
and the offset (nonchanging component) capacitance of up to 10
pF can be balanced by a programmable on-chip CAPDAC.
0x000 TO 0xFFF
DATA
CIN
EXC
CAPDAC
10pF
0pF TO 4pF
CDC
C
SENS
10pF TO 14pF
07086-012
Figure 22. Using CAPDAC
The CAPDAC can be understood as a negative capacitance
connected internally to the CIN pin. The CAPDAC has a 6-bit
resolution and a monotonic transfer function.
Figure 22 shows
how to use the CAPDAC to shift the CDC 4 pF input range to
measure capacitance between 10 pF and 14 pF.
AD7151
Rev. 0 | Page 11 of 28
COMPARATOR AND THRESHOLD MODES
The AD7151 comparator and its threshold can be programmed
to operate in several different modes. In an adaptive mode, the
threshold is dynamically adjusted and the comparator output
indicates fast changes and ignores slow changes in the input
(sensor) capacitance. Alternatively, the threshold can be
programmed as a constant (fixed) value, and the output then
indicates any change in the input capacitance that crosses the
defined fixed threshold.
The AD7151 logic output (active high) indicates either a positive or
a negative change in the input capacitance, in both adaptive and
fixed threshold modes (see
Figure 23 and Figure 24).
POSITIVE
THRESHOLD
INPUT
CAPACITANCE
OUTPUT
OUTPUT ACTIVE
TIME
POSITIVE CHANGE
0
7086-013
Figure 23. Positive Threshold Mode
Indicates Positive Change in Input Capacitance
NEGATIVE
THRESHOLD
INPUT
CAPACITANCE
OUTPUT
OUTPUT ACTIVE
TIME
NEGATIVE CHANGE
0
7086-014
Figure 24. Negative Threshold Mode
Indicates Negative Change in Input Capacitance
Additionally, for the adaptive mode only, the comparator can
work as window comparator, indicating input either inside or
outside a selected sensitivity band (see
Figure 25 and Figure 26).
POSITIVE
THRESHOLD
NEGATIVE
THRESHOLD
INPUT CAPACITANCE
OUTPUT
OUTPUT ACTIVE
TIME
INPUT INSIDE THRESHOLD WINDOW
0
7086-015
Figure 25. In-Window (Adaptive) Threshold Mode
POSITIVE
THRESHOLD
NEGATIVE
THRESHOLD
INPUT CAPACITANCE
OUTPUT
OUTPUT ACTIVE
TIME
INPUT OUTSIDE THRESHOLD WINDOW
07086-016
Figure 26. Out-Window (Adaptive) Threshold Mode
ADAPTIVE THRESHOLD
In an adaptive mode, the thresholds are dynamically adjusted,
ensuring indication of fast changes (for example an object
moving close to a capacitive proximity sensor) and eliminating
slow changes in the input (sensor) capacitance, usually caused
by environment changes such as humidity or temperature or
changes in the sensor dielectric material over time (see
Figure 27).
THRESHOLD
INPUT CAPACITANCE
OUTPUT
OUTPUT ACTIVE
TIME
FAST CHANGE
SLOW CHANGE
07086-017
Figure 27. Adaptive Threshold
Indicates Fast Changes and Eliminates Slow Changes in Input Capacitance
DATA AVERAGE
The adaptive threshold algorithm is based on an average calculated
from previous CDC output data. The response of the average to an
input capacitance step change (more exactly, response to the change
in the CDC output data) is an exponential settling curve, which can
be characterized by the following equation:
)1()0()(
/TimeConstN
eChangeAverageNAverage +=
where:
Average(N) is the value of average N complete CDC conversion
cycles after a step change on the input.
Average(0) is the value before the step change.
TimeConst can be selected in the range between 2 and 65,536, in
steps of power of 2, by programming the ThrSettling bits in the
setup register.
See
Figure 28 and the Register Descriptions section.
INPUT CAPACITANCE
(CDC DATA) CHANGE
DATA AVERAGE RESPONSE
TIME
07086-018
Figure 28. Data Average Response to Data Step Change

AD7151BRMZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 1-CH Cap Proximity Sensor Inter IC
Lifecycle:
New from this manufacturer.
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