AD7151
Rev. 0 | Page 18 of 28
SETUP REGISTER
Address Pointer 0x0B
8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic RngH RngL
Hyst
ThrSettling (4-Bit Value)
Default 0 0 0 0 0x0B
Table 11. Setup Register Bit Descriptions
Bit Mnemonic Description
Range bits set the CDC input range and determine the step for the AutoDAC function.
RngH RngL Capacitive Input Range (pF) AutoDAC Step (CAPDAC LSB)
0 0 2 4
0 1 0.5 1
1 0 1 2
7
6
RngH
RngL
1 1 4 8
5 This bit should be 0 for the specified operation.
4
Hyst Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode;
hysteresis is always disabled in the fixed threshold mode.
3
2
1
0
ThrSettling
Determines the settling time constant of the data average and thus the settling time of the adaptive
thresholds.
The response of the average to an input capacitance step change (that is, response to the change in the CDC
output data) is an exponential settling curve characterized by the following equation:
)1()0()(
/ TimeConstN
eChangeAverageNAverage +=
where:
Average(N) is the value of average N complete CDC conversion cycles after a step change on the input
Average(0) is the value before the step change
TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of
2, by programming the ThrSettling bits.
)1(
2
+
=
gThrSettlin
TimeConst
See
Figure 39.
INPUT CAPACITANCE
(CDC DATA) CHANGE
DATA AVERAGE RESPONSE
TIME
07086-028
Figure 39. Data Average Response to Data Step Change
AD7151
Rev. 0 | Page 19 of 28
CONFIGURATION REGISTER
Address Pointer 0x0F
8 Bits, Read/Write, Factory Preset 0x19
Table 12. Configuration Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic ThrFixed ThrMD1 ThrMD0 EnConv MD2 MD1 MD0
Default 0 0 0 1 0 0 0 1
Table 13.Configuration Register Bit Descriptions
Bit Mnemonic Description
7 ThrFixed
ThrFixed = 1 sets the fixed threshold mode. The output reflects comparison of data and a fixed (constant) value
of the threshold register.
ThrFixed = 0 sets the adaptive threshold mode. The output reflects comparison of data to the adaptive
threshold. The adaptive threshold is set dynamically, based on the history of the previous data.
These bits set the output comparator mode.
Output Active When
ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode
0 0 Negative data < average – sensitivity Data < Threshold
0 1 Positive data > average + sensitivity Data > Threshold
1 0 In-Window data > average – sensitivity
AND
data < average + sensitivity
-
6
5
ThrMD1
ThrMD0
1 1 Out-Window data < average – sensitivity
OR
data > average + sensitivity
-
4 EnConv Enables conversion. This bit must be 1 for proper operation.
3 This bit must be 0 for proper operation.
Converter mode of operation setup.
MD2 MD1 MD0 Mode Description
0 0 0 Idle Part is fully powered up but performing no conversion.
0 0 1
Continuous
Conversion
Part is repeatedly performing conversions, provided the
EnConv bit is set.
0 1 0 Single Conversion
Part performs a single conversion, provided the EnConv bit
is set. After finishing the conversion(s), the part goes to the
idle mode.
0 1 1 Power-Down
Powers down the on-chip circuits, except the digital
interface.
2
1
0
MD2
MD1
MD0
1 X X Reserved Do not use these modes.
AD7151
Rev. 0 | Page 20 of 28
POWER-DOWN TIMER REGISTER
Address Pointer 0x10
8 Bits, Read/Write, Factory Preset 0x00
Table 14. Power-Down Timer Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic Power-Down Timeout (6-Bit Value)
Default 0 0 0x00
Table 15. Power-Down Timer Register Bit Descriptions
Bit Mnemonic Description
[7:6] - These bits must be 0 for proper operation
[5:0]
Power-Down
Timeout
Defines the period duration of the power-down timeout.
If the output comparator output has not been activated during the programmed period, the part enters power-
down mode automatically. The part can be then returned to a normal operational mode either via the serial
interface or by the power supply off/on sequence.
The period is programmable in steps of four hours. For example, setting the value to 0x06 sets the duration to
24 hours. The maximum value of 0x3F corresponds to approximately 10.5 days.
The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode
automatically.
CAPDAC REGISTER
Address Pointer 0x11
8 Bits, Read/Write, Factory Preset 0x00
Table 16. CAPDAC Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic DacEn DacAuto DacValue (6-Bit Value)
Default 1 1 0x00
Table 17. CAPDAC Register Bit Descriptions
Bit Mnemonic Description
7 DacEn DacEn = 1 enables capacitive DAC.
6 DacAuto DacAuto = 1 enables the AutoDAC function in the adaptive threshold mode.
When the AutoDAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an
optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average
exceeds ¾ of the CDC full range, and the CAPDAC value is decremented when the data average goes below ¼
of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive
input range.
Bit has no effect in fixed threshold mode; the AutoDAC function is always disabled in the fixed threshold mode.
[5:0] DacValue
CAPDAC value, Code 0x00
0 pF, Code 0x3F CAPDAC full range.
SERIAL NUMBER REGISTER
Address Pointer 0x13, 0x14, 0x15, 0x16
32 Bits, Read Only, 0xXXXX
This register holds a serial number, unique for each individual part.
CHIP ID REGISTER
Address Pointer 0x17
8 Bits, Read Only, 0xXX
This register holds the chip identification code, used in factory
manufacturing and testing.

AD7151BRMZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 1-CH Cap Proximity Sensor Inter IC
Lifecycle:
New from this manufacturer.
Delivery:
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