AD7151
Rev. 0 | Page 4 of 28
Parameter Min Typ Max Unit
1
Test Conditions/Comments
POWER REQUIREMENTS
V
DD
-to-GND Voltage 2.7 3.6 V V
DD
= 3.3 V, nominal
I
DD
Current
4
70 80 μA
I
DD
Current Power-Down Mode
4
1 5 μA Temperature ≤ 25°C
3 10 μA Temperature = 85°C
1
Capacitance units: one picofarad (1 pF) = 1 × 10
−12
farad (F); one femtofarad (1 fF) = 10
−15
farad (F).
2
The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion
input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC
nominal input range.
3
Specification is not production tested but is supported by characterization data at initial product release.
4
Digital inputs equal to V
DD
or GND.
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V
DD
; –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
CONVERTER
Conversion Time 10 ms
Wake-Up Time from Power-Down Mode
1, 2
0.3 ms
Power-Up Time
1, 3
2 ms
Reset Time
1, 4
2 ms
SERIAL INTERFACE
5, 6
See Figure 2.
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 μs
SCL Low Pulse Width, t
LOW
1.3 μs
SCL, SDA Rise Time, t
R
0.3 μs
SCL, SDA Fall Time, t
F
0.3 μs
Hold Time (Start Condition), t
HD;STA
0.6 μs After this period, the first clock is generated.
Setup Time (Start Condition), t
SU;STA
0.6 μs Relevant for repeated start condition.
Data Setup Time, t
SU;DAT
0.1 μs
Setup Time (Stop Condition), t
SU;STO
0.6 μs
Data Hold Time (Master), t
HD;DAT
10 ns
Bus-Free Time (Between Stop and Start Condition), t
BUF
1.3 μs
1
Specification is not production tested but is supported by characterization data at initial product release.
2
Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
3
Power-up time is the maximum delay between the V
DD
crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface
command.
4
Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface
command.
5
Sample tested during initial release to ensure compliance.
6
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
SU;STO
t
HIGH
SCL
PS
SDA
t
BUF
07086-002
Figure 2. Serial Interface Timing Diagram
