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ISL6545IBZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
4
FN6305.6
March 3, 2011
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V
BOOT Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . GND - 0.3V to 36V
UGATE Voltage V
UGATE
. . . . . . . .V
PHASE
- 0.3V to V
BOOT
+ 0.3V
V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
BOOT
+0.3V
LGATE/OCSET Voltage, V
LGATE/OCSET
GND - 0.3V to V
CC
+ 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to V
CC
+ 0.3V
PHASE Voltage, V
PHASE
. . . . . . . . . .GND - 0.3V to V
BOOT
+ 0.3V
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
BOOT-GND
<36V)
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . . .15V
-0.3V to 16V (<10ns, 10µJ)
Clamp Voltage, V
BOOT
- V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . .24V
FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6V
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV
Thermal Resistance θ
JA
(°C/W) θ
JC
(°C/W)
SOIC Package (Note 4). . . . . . . . . . . . . . 95 N/A
DFN Package (Notes 5, 6). . . . . . . . . . . . 44 5.5
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage, V
CC
. . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V
Ambient Temperature Range
ISL6545C, ISL6545AC. . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6545I, ISL6545AI . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See
Tech Brief TB379
for details.
6. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications V
CC
= 12V, T
J
= 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNITS
V
CC
SUPPLY CURRENT
Input Bias Supply Current I
VCC
V
CC
= 12V; disabled 4 5.2 7 mA
POWER-ON RESET
Rising V
CC
POR Threshold V
POR
3.9 4.1 4.3 V
V
CC
POR Threshold Hysteresis 0.30 0.35 0.40 V
OSCILLATOR
Switching Frequency f
OSC
ISL6545C 270 300 330 kHz
ISL6545I 240 300 330 kHz
f
OSC
ISL6545AC 540 600 660 kHz
ISL6545AI 510 600 660 kHz
Ramp Amplitude ΔV
OSC
1.5 V
P-P
REFERENCE
Reference Voltage Tolerance ISL6545C -1.0 - +1.0 %
ISL6545I -1.5 - +1.5 %
Nominal Reference Voltage V
REF
0.600 V
ERROR AMPLIFIER
DC Gain GAIN 96 dB
Gain-Bandwidth Product GBWP 20 MHz
Slew Rate SR 9 V/µs
GATE DRIVERS
Upper Gate Source Impedance R
UG-SRCh
V
CC
= 14.5V; I = 50mA 3.0 Ω
Upper Gate Sink Impedance R
UG-SNKh
V
CC
= 14.5V; I = 50mA 2.7 Ω
Lower Gate Source Impedance R
LG-SRCh
V
CC
= 14.5V; I = 50mA 2.4 Ω
Lower Gate Sink Impedance R
LG-SNKh
V
CC
= 14.5V; I = 50mA 2.0 Ω
ISL6545, ISL6545A
5
FN6305.6
March 3, 2011
Functional Pin Description (SOIC, DFN)
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545x, as well
as the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if V
CC
rises above 6.5V (but the LGATE/OCSET and
BOOT will still be sourced by VCC). Connect a well-
decoupled 5V or 12V supply to this pin.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package,
Pin 4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-channel MOSFET (equal to V
CC
minus
the on-chip BOOT diode voltage drop), with respect to PHASE.
COMP/SD (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (V
DISABLE
= 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the V
DISABLE
trip point, the
ISL6545x will begin a new Initialization and soft-start cycle.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from V
CC
). This pin is also
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (R
OCSET
) from this pin to GND. See
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
Upper Gate Source Impedance R
UG-SRCl
V
CC
= 4.25V; I = 50mA 3.5 Ω
Upper Gate Sink Impedance R
UG-SNKl
V
CC
= 4.25V; I = 50mA 2.7 Ω
Lower Gate Source Impedance R
LG-SRCl
V
CC
= 4.25V; I = 50mA 2.75 Ω
Lower Gate Sink Impedance R
LG-SNKl
V
CC
= 4.25V; I = 50mA 2.1 Ω
PROTECTION/DISABLE
OCSET Current Source I
OCSET
ISL6545C; LGATE/OCSET = 0V 19.5 21.5 23.5 µA
ISL6545I; LGATE/OCSET = 0V 18.0 21.5 23.5 µA
Disable Threshold (COMP/SD pin) V
DISABLE
0.375 0.400 0.425 V
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications V
CC
= 12V, T
J
= 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNITS
ISL6545, ISL6545A
6
FN6305.6
March 3, 2011
Functional Description
Initialization (POR and OCP Sampling)
Figure 1 shows a simplified timing diagram. The
Power-On-Reset (POR) function continually monitors the
bias voltage at the VCC pin. Once the rising POR threshold
is exceeded (VPOR ~4V nominal), the POR function initiates
the Overcurrent Protection (OCP) sample and hold
operation (while COMP/SD is ~1V). When the sampling is
complete, VOUT begins the soft-start ramp.
If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
voltage is above the V
DISABLE
trip point.
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either V
CC
rises above
V
POR
, or the COMP/SD pin is released (after POR). The
COMP/SD will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/SD
exceeds the V
DISABLE
trip point (at t1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/SD pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/SD will continue to ramp to ~1V.
From t1, there is a nominal 6.8ms delay, which allows the
V
CC
pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
time, the LGATE/OCSET pin is initialized, by disabling the
LGATE driver and drawing I
OCSET
(nominal 21.5µA)
through R
OCSET
. This sets up a voltage that will represent
the OCSET trip point. At t2, there is a variable time period for
the OCP sample and hold operation (0ms to 3.4ms nominal;
the longer time occurs with the higher overcurrent setting).
The sample and hold uses a digital counter and DAC to save
the voltage, so the stored value does not degrade, for as
long as the V
CC
is above V
POR
. See “Overcurrent Protection
(OCP)” on page 7 for more details on the equations and
variables. Upon the completion of sample and hold at t3, the
soft-start operation is initiated, and the output voltage ramps
up between t4 and t5.
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on
the non-inverting terminal of the error amp from 0V to 0.6V in
a nominal 6.8ms The output voltage will thus follow the
ramp, from zero to final value, in the same 6.8ms (the actual
ramp seen on the V
OUT
will be less than the nominal time,
due to some initialization timing, between t3 and t4).
The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally, and it is the same for either frequency
version of the IC (300kHz or 600kHz).
After an initialization period (t3 to t4), the error amplifier
(COMP/SD pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error
amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitors. When the
internally generated soft-start voltage exceeds the reference
voltage (0.6V), the soft-start is complete, and the output
should be in regulation at the expected voltage. This method
provides a rapid and controlled output voltage rise; there is
no large inrush current charging the output capacitors. The
entire start-up sequence from POR typically takes up to
17ms; up to 10.2ms for the delay and OCP sample, and
6.8ms for the soft-start ramp.
Figure 3 shows the normal curve in blue; initialization begins
at t0, and the output ramps between t1 and t2. If the output is
pre-biased to a voltage less than the expected value, as
shown by the magenta curve, the ISL6545x will detect that
condition. Neither MOSFET will turn on until the soft-start
ramp voltage exceeds the output; V
OUT
starts seamlessly
ramping from there. If the output is pre-biased to a voltage
above the expected value, as in the red curve, neither
MOSFET will turn on until the end of the soft-start, at which
COMP/SD (1V/DIV)
V
OUT
(1V/DIV)
V
CC
(2V/DIV)
GND>
FIGURE 1. POR AND SOFT-START OPERATION
~4V POR
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
0.4V
COMP/SD (0.25V/DIV)
LGATE/OCSET (0.25V/DIV)
LGATE
STARTS
SWITCHING
3.4ms3.4ms 0 - 3.4ms
6.8ms
V
OUT
(0.5V/DIV)
GND>
t0 t1 t2 t3 t4 t5
ISL6545, ISL6545A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ISL6545IBZ-T

Mfr. #:
Buy ISL6545IBZ-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 8LD SYNC PWM BUCK CNTRLR 300KHZ
Lifecycle:
New from this manufacturer.
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