Philips Semiconductors Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
14
Data format
Table 2. Format of programmed data
Last In MSB Serial Programming Format First In LSB
p23 p22 p21 p20 ../.. ../.. p1 p0
Table 3. A word, length 24 bits
Last In MSB LSB First In
Address fmod Fractional-N Main Divider ratio Spare
0 0 fmod NF2 NF1 NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 SK1 SK2
Default
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
A word address Fixed to 00.
Fractional Modulus select fmod = 0 is modulo 8; fmod = 1 is modulo 5.
Fractional-N Increment Fractional-N Increment values 000 to 111 (0 to 7). NF is a 3-bit word.
N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Spare SK1, SK2 must be set to 0.
Table 4. B word, length 24 bits
Address Reference Divider Lock PD FDAC (Fractional Compensation DAC)
0 1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L1 L0 Main Aux FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
Default
0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0
B word address Fixed to 01
REF-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ratio. R <9:0>.
Lock detect output L1 L0
0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull).
0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain).
1 0 Main lock detect signal present at the LOCK pin (push/pull).
1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull).
When auxiliary loop and main loop are in power down mode, the lock indicator is low.
Power down (PD)
PON pin is tied to GND Main = 1: power-on to Main PLL. Main = 0: power-down to Main PLL.
Aux = 1: power-on to Aux PLL. Aux = 0: power-down to Aux PLL.
PON pin is tied to V
DD
Main = 0: power-on to Main PLL. Main = 1: power-down to Main PLL.
Aux = 0: power-on to Aux PLL. Aux = 1: power-down to Aux PLL.
Fractional Compensation FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 5. C word, length 24 bits
Address Auxiliary Divider CP SM SA
1 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CP1 CP0 SM2 SM1 SM0 SA2 SA1 SA0
Default
0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0
C word address Fixed to 10
A-Divider A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.
Charge pump current Ratio CP1, CP0: Charge pump current ratio, see Table 1.
Main comparison select SM comparison divider select for main phase detector.
Aux comparison select SA Comparison divider select for auxiliary phase detector.
Table 6. D word, length 24 bits
Address Synthesizer Test Bits
1 1 0 – – – – T
dis-spu
Tspu – – – – – – – – – – – – – – –
Default
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D word address Fixed to 110.
T
dis-spu
= 1 Speed-up mode disabled. NOTE: All other test bits must be set to 0 for normal operation.
T
spu
= 1 Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation.
