Philips Semiconductors Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
8
1.0 FUNCTIONAL DESCRIPTION
1.1 Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18 dBm to
0 dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65535.
The fractional modulus is selected by programming FMOD in the
A word. There are 2 modulus to select from: when FMOD = 0,
modulo 8 is selected; when FMOD = 1, modulo 5 is selected.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1, to N + 1. The average division ratio over modulo main divider
cycles (either 5 or 8) will be
Nfrac +
ǒ
N )
NF
f
MOD
Ǔ
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump. Thus, f
VCO
= f
comp
*
ǒ
N )
NF
f
MOD
Ǔ
.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
1.2 Auxiliary divider
The AUXin input drives a pre-amplifier to provide the clock to the
first divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The circuit operates with
signal levels from –15 dBm to 0 dBm (112 to 632 mVpp), and at
frequencies as high as 550 MHz. The divider consists of a fully
programmable bipolar prescaler followed by a CMOS counter. Total
divide ratios range from 128 to 16383.
1.3 Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 6) determines which one of
the 5 output pulses are selected as the main (auxiliary) phase
detector input, thus allowing the main PFD and auxiliary PFD to
operate at different frequencies.
1.4 Phase detector (see Figure 7)
The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Table 1). The dead zone (caused
by finite time taken to switch the current sources on or off) is
cancelled by forcing the pumps ON for a minimum time (τ) at every
cycle (backlash time) providing improved linearity.
SR01415
DIVIDE BY R /2 /2 /2 /2
REFERENCE
INPUT
SM=”000”
SM=”001”
SM=”010”
SM=”011”
SM=”100”
SA=”100”
SA=”011”
SA=”010”
SA=”001”
SA=”000”
TO
MAIN
PHASE
DETECTOR
TO
AUXILIARY
PHASE
DETECTOR
Figure 6. Reference Divider
